2 * Copyright (c) 2011-2013 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
46 #ifndef __CPU_BASE_HH__
47 #define __CPU_BASE_HH__
51 // Before we do anything else, check if this build is the NULL ISA,
52 // and if so stop here
53 #include "config/the_isa.hh"
54 #if THE_ISA == NULL_ISA
55 #include "arch/null/cpu_dummy.hh"
57 #include "arch/interrupts.hh"
58 #include "arch/isa_traits.hh"
59 #include "arch/microcode_rom.hh"
60 #include "base/statistics.hh"
61 #include "mem/mem_object.hh"
62 #include "sim/eventq.hh"
63 #include "sim/full_system.hh"
64 #include "sim/insttracer.hh"
65 #include "sim/system.hh"
71 class CPUProgressEvent : public Event
80 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
84 void interval(Tick ival) { _interval = ival; }
85 Tick interval() { return _interval; }
87 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
89 virtual const char *description() const;
92 class BaseCPU : public MemObject
96 // @todo remove me after debugging with legion done
98 // every cpu has an id, put it in the base cpu
99 // Set at initialization, only time a cpuId might change is during a
100 // takeover (which should be done from within the BaseCPU anyway,
101 // therefore no setCpuId() method is provided
104 /** instruction side request id that must be placed in all requests */
105 MasterID _instMasterId;
107 /** data side request id that must be placed in all requests */
108 MasterID _dataMasterId;
110 /** An intrenal representation of a task identifier within gem5. This is
111 * used so the CPU can add which taskId (which is an internal representation
112 * of the OS process ID) to each request so components in the memory system
113 * can track which process IDs are ultimately interacting with them
117 /** The current OS process ID that is executing on this processor. This is
118 * used to generate a taskId */
121 /** Is the CPU switched out or active? */
124 /** Cache the cache line size that we get from the system */
125 const unsigned int _cacheLineSize;
130 * Purely virtual method that returns a reference to the data
131 * port. All subclasses must implement this method.
133 * @return a reference to the data port
135 virtual MasterPort &getDataPort() = 0;
138 * Purely virtual method that returns a reference to the instruction
139 * port. All subclasses must implement this method.
141 * @return a reference to the instruction port
143 virtual MasterPort &getInstPort() = 0;
145 /** Reads this CPU's ID. */
146 int cpuId() { return _cpuId; }
148 /** Reads this CPU's unique data requestor ID */
149 MasterID dataMasterId() { return _dataMasterId; }
150 /** Reads this CPU's unique instruction requestor ID */
151 MasterID instMasterId() { return _instMasterId; }
154 * Get a master port on this CPU. All CPUs have a data and
155 * instruction port, and this method uses getDataPort and
156 * getInstPort of the subclasses to resolve the two ports.
158 * @param if_name the port name
159 * @param idx ignored index
161 * @return a reference to the port with the given name
163 BaseMasterPort &getMasterPort(const std::string &if_name,
164 PortID idx = InvalidPortID);
166 /** Get cpu task id */
167 uint32_t taskId() const { return _taskId; }
168 /** Set cpu task id */
169 void taskId(uint32_t id) { _taskId = id; }
171 uint32_t getPid() const { return _pid; }
172 void setPid(uint32_t pid) { _pid = pid; }
174 inline void workItemBegin() { numWorkItemsStarted++; }
175 inline void workItemEnd() { numWorkItemsCompleted++; }
176 // @todo remove me after debugging with legion done
177 Tick instCount() { return instCnt; }
179 TheISA::MicrocodeRom microcodeRom;
182 TheISA::Interrupts *interrupts;
186 getInterruptController()
191 virtual void wakeup() = 0;
194 postInterrupt(int int_num, int index)
196 interrupts->post(int_num, index);
202 clearInterrupt(int int_num, int index)
204 interrupts->clear(int_num, index);
210 interrupts->clearAll();
214 checkInterrupts(ThreadContext *tc) const
216 return FullSystem && interrupts->checkInterrupts(tc);
219 class ProfileEvent : public Event
226 ProfileEvent(BaseCPU *cpu, Tick interval);
229 ProfileEvent *profileEvent;
232 std::vector<ThreadContext *> threadContexts;
234 Trace::InstTracer * tracer;
238 // Mask to align PCs to MachInst sized boundaries
239 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
241 /// Provide access to the tracer pointer
242 Trace::InstTracer * getTracer() { return tracer; }
244 /// Notify the CPU that the indicated context is now active. The
245 /// delay parameter indicates the number of ticks to wait before
246 /// executing (typically 0 or 1).
247 virtual void activateContext(ThreadID thread_num, Cycles delay) {}
249 /// Notify the CPU that the indicated context is now suspended.
250 virtual void suspendContext(ThreadID thread_num) {}
252 /// Notify the CPU that the indicated context is now deallocated.
253 virtual void deallocateContext(ThreadID thread_num) {}
255 /// Notify the CPU that the indicated context is now halted.
256 virtual void haltContext(ThreadID thread_num) {}
258 /// Given a Thread Context pointer return the thread num
259 int findContext(ThreadContext *tc);
261 /// Given a thread num get tho thread context for it
262 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
265 typedef BaseCPUParams Params;
266 const Params *params() const
267 { return reinterpret_cast<const Params *>(_params); }
268 BaseCPU(Params *params, bool is_checker = false);
272 virtual void startup();
273 virtual void regStats();
275 virtual void activateWhenReady(ThreadID tid) {};
277 void registerThreadContexts();
280 * Prepare for another CPU to take over execution.
282 * When this method exits, all internal state should have been
283 * flushed. After the method returns, the simulator calls
284 * takeOverFrom() on the new CPU with this CPU as its parameter.
286 virtual void switchOut();
289 * Load the state of a CPU from the previous CPU object, invoked
290 * on all new CPUs that are about to be switched in.
292 * A CPU model implementing this method is expected to initialize
293 * its state from the old CPU and connect its memory (unless they
294 * are already connected) to the memories connected to the old
297 * @param cpu CPU to initialize read state from.
299 virtual void takeOverFrom(BaseCPU *cpu);
302 * Flush all TLBs in the CPU.
304 * This method is mainly used to flush stale translations when
305 * switching CPUs. It is also exported to the Python world to
306 * allow it to request a TLB flush after draining the CPU to make
307 * it easier to compare traces when debugging
308 * handover/checkpointing.
313 * Determine if the CPU is switched out.
315 * @return True if the CPU is switched out, false otherwise.
317 bool switchedOut() const { return _switchedOut; }
320 * Verify that the system is in a memory mode supported by the
323 * Implementations are expected to query the system for the
324 * current memory mode and ensure that it is what the CPU model
325 * expects. If the check fails, the implementation should
326 * terminate the simulation using fatal().
328 virtual void verifyMemoryMode() const { };
331 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
332 * This is a constant for the duration of the simulation.
337 * Vector of per-thread instruction-based event queues. Used for
338 * scheduling events based on number of instructions committed by
339 * a particular thread.
341 EventQueue **comInstEventQueue;
344 * Vector of per-thread load-based event queues. Used for
345 * scheduling events based on number of loads committed by
346 *a particular thread.
348 EventQueue **comLoadEventQueue;
353 * Get the cache line size of the system.
355 inline unsigned int cacheLineSize() const { return _cacheLineSize; }
358 * Serialize this object to the given output stream.
360 * @note CPU models should normally overload the serializeThread()
361 * method instead of the serialize() method as this provides a
362 * uniform data format for all CPU models and promotes better code
365 * @param os The stream to serialize to.
367 virtual void serialize(std::ostream &os);
370 * Reconstruct the state of this object from a checkpoint.
372 * @note CPU models should normally overload the
373 * unserializeThread() method instead of the unserialize() method
374 * as this provides a uniform data format for all CPU models and
375 * promotes better code reuse.
377 * @param cp The checkpoint use.
378 * @param section The section name of this object.
380 virtual void unserialize(Checkpoint *cp, const std::string §ion);
383 * Serialize a single thread.
385 * @param os The stream to serialize to.
386 * @param tid ID of the current thread.
388 virtual void serializeThread(std::ostream &os, ThreadID tid) {};
391 * Unserialize one thread.
393 * @param cp The checkpoint use.
394 * @param section The section name of this thread.
395 * @param tid ID of the current thread.
397 virtual void unserializeThread(Checkpoint *cp, const std::string §ion,
400 virtual Counter totalInsts() const = 0;
402 virtual Counter totalOps() const = 0;
405 * Schedule an event that exits the simulation loops after a
406 * predefined number of instructions.
408 * This method is usually called from the configuration script to
409 * get an exit event some time in the future. It is typically used
410 * when the script wants to simulate for a specific number of
411 * instructions rather than ticks.
413 * @param tid Thread monitor.
414 * @param insts Number of instructions into the future.
415 * @param cause Cause to signal in the exit event.
417 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
420 * Schedule an event that exits the simulation loops after a
421 * predefined number of load operations.
423 * This method is usually called from the configuration script to
424 * get an exit event some time in the future. It is typically used
425 * when the script wants to simulate for a specific number of
426 * loads rather than ticks.
428 * @param tid Thread monitor.
429 * @param loads Number of load instructions into the future.
430 * @param cause Cause to signal in the exit event.
432 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
436 bool functionTracingEnabled;
437 std::ostream *functionTraceStream;
438 Addr currentFunctionStart;
439 Addr currentFunctionEnd;
440 Tick functionEntryTick;
441 void enableFunctionTrace();
442 void traceFunctionsInternal(Addr pc);
445 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
448 void traceFunctions(Addr pc)
450 if (functionTracingEnabled)
451 traceFunctionsInternal(pc);
454 static int numSimulatedCPUs() { return cpuList.size(); }
455 static Counter numSimulatedInsts()
459 int size = cpuList.size();
460 for (int i = 0; i < size; ++i)
461 total += cpuList[i]->totalInsts();
466 static Counter numSimulatedOps()
470 int size = cpuList.size();
471 for (int i = 0; i < size; ++i)
472 total += cpuList[i]->totalOps();
478 // Number of CPU cycles simulated
479 Stats::Scalar numCycles;
480 Stats::Scalar numWorkItemsStarted;
481 Stats::Scalar numWorkItemsCompleted;
484 #endif // THE_ISA == NULL_ISA
486 #endif // __CPU_BASE_HH__