src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011-2013, 2017, 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_BASE_HH__
  43 #define __CPU_BASE_HH__
  44
  45 #include <vector>
  46
  47 // Before we do anything else, check if this build is the NULL ISA,
  48 // and if so stop here
  49 #include "config/the_isa.hh"
  50 #if THE_ISA == NULL_ISA
  51 #include "arch/null/cpu_dummy.hh"
  52 #else
  53 #include "arch/generic/interrupts.hh"
  54 #include "arch/isa_traits.hh"
  55 #include "arch/microcode_rom.hh"
  56 #include "base/statistics.hh"
  57 #include "mem/port_proxy.hh"
  58 #include "sim/clocked_object.hh"
  59 #include "sim/eventq.hh"
  60 #include "sim/full_system.hh"
  61 #include "sim/insttracer.hh"
  62 #include "sim/probe/pmu.hh"
  63 #include "sim/probe/probe.hh"
  64 #include "sim/system.hh"
  65 #include "debug/Mwait.hh"
  66
  67 class BaseCPU;
  68 struct BaseCPUParams;
  69 class CheckerCPU;
  70 class ThreadContext;
  71
  72 struct AddressMonitor
  73 {
  74     AddressMonitor();
  75     bool doMonitor(PacketPtr pkt);
  76
  77     bool armed;
  78     Addr vAddr;
  79     Addr pAddr;
  80     uint64_t val;
  81     bool waiting;   // 0=normal, 1=mwaiting
  82     bool gotWakeup;
  83 };
  84
  85 class CPUProgressEvent : public Event
  86 {
  87   protected:
  88     Tick _interval;
  89     Counter lastNumInst;
  90     BaseCPU *cpu;
  91     bool _repeatEvent;
  92
  93   public:
  94     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  95
  96     void process();
  97
  98     void interval(Tick ival) { _interval = ival; }
  99     Tick interval() { return _interval; }
 100
 101     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 102
 103     virtual const char *description() const;
 104 };
 105
 106 class BaseCPU : public ClockedObject
 107 {
 108   protected:
 109
 110     /// Instruction count used for SPARC misc register
 111     /// @todo unify this with the counters that cpus individually keep
 112     Tick instCnt;
 113
 114     // every cpu has an id, put it in the base cpu
 115     // Set at initialization, only time a cpuId might change is during a
 116     // takeover (which should be done from within the BaseCPU anyway,
 117     // therefore no setCpuId() method is provided
 118     int _cpuId;
 119
 120     /** Each cpu will have a socket ID that corresponds to its physical location
 121      * in the system. This is usually used to bucket cpu cores under single DVFS
 122      * domain. This information may also be required by the OS to identify the
 123      * cpu core grouping (as in the case of ARM via MPIDR register)
 124      */
 125     const uint32_t _socketId;
 126
 127     /** instruction side request id that must be placed in all requests */
 128     MasterID _instMasterId;
 129
 130     /** data side request id that must be placed in all requests */
 131     MasterID _dataMasterId;
 132
 133     /** An intrenal representation of a task identifier within gem5. This is
 134      * used so the CPU can add which taskId (which is an internal representation
 135      * of the OS process ID) to each request so components in the memory system
 136      * can track which process IDs are ultimately interacting with them
 137      */
 138     uint32_t _taskId;
 139
 140     /** The current OS process ID that is executing on this processor. This is
 141      * used to generate a taskId */
 142     uint32_t _pid;
 143
 144     /** Is the CPU switched out or active? */
 145     bool _switchedOut;
 146
 147     /** Cache the cache line size that we get from the system */
 148     const unsigned int _cacheLineSize;
 149
 150   public:
 151
 152     /**
 153      * Purely virtual method that returns a reference to the data
 154      * port. All subclasses must implement this method.
 155      *
 156      * @return a reference to the data port
 157      */
 158     virtual Port &getDataPort() = 0;
 159
 160     /**
 161      * Returns a sendFunctional delegate for use with port proxies.
 162      */
 163     virtual PortProxy::SendFunctionalFunc
 164     getSendFunctional()
 165     {
 166         auto port = dynamic_cast<MasterPort *>(&getDataPort());
 167         assert(port);
 168         return [port](PacketPtr pkt)->void { port->sendFunctional(pkt); };
 169     }
 170
 171     /**
 172      * Purely virtual method that returns a reference to the instruction
 173      * port. All subclasses must implement this method.
 174      *
 175      * @return a reference to the instruction port
 176      */
 177     virtual Port &getInstPort() = 0;
 178
 179     /** Reads this CPU's ID. */
 180     int cpuId() const { return _cpuId; }
 181
 182     /** Reads this CPU's Socket ID. */
 183     uint32_t socketId() const { return _socketId; }
 184
 185     /** Reads this CPU's unique data requestor ID */
 186     MasterID dataMasterId() const { return _dataMasterId; }
 187     /** Reads this CPU's unique instruction requestor ID */
 188     MasterID instMasterId() const { return _instMasterId; }
 189
 190     /**
 191      * Get a port on this CPU. All CPUs have a data and
 192      * instruction port, and this method uses getDataPort and
 193      * getInstPort of the subclasses to resolve the two ports.
 194      *
 195      * @param if_name the port name
 196      * @param idx ignored index
 197      *
 198      * @return a reference to the port with the given name
 199      */
 200     Port &getPort(const std::string &if_name,
 201                   PortID idx=InvalidPortID) override;
 202
 203     /** Get cpu task id */
 204     uint32_t taskId() const { return _taskId; }
 205     /** Set cpu task id */
 206     void taskId(uint32_t id) { _taskId = id; }
 207
 208     uint32_t getPid() const { return _pid; }
 209     void setPid(uint32_t pid) { _pid = pid; }
 210
 211     inline void workItemBegin() { numWorkItemsStarted++; }
 212     inline void workItemEnd() { numWorkItemsCompleted++; }
 213     // @todo remove me after debugging with legion done
 214     Tick instCount() { return instCnt; }
 215
 216     TheISA::MicrocodeRom microcodeRom;
 217
 218   protected:
 219     std::vector<BaseInterrupts*> interrupts;
 220
 221   public:
 222     BaseInterrupts *
 223     getInterruptController(ThreadID tid)
 224     {
 225         if (interrupts.empty())
 226             return NULL;
 227
 228         assert(interrupts.size() > tid);
 229         return interrupts[tid];
 230     }
 231
 232     virtual void wakeup(ThreadID tid) = 0;
 233
 234     void
 235     postInterrupt(ThreadID tid, int int_num, int index);
 236
 237     void
 238     clearInterrupt(ThreadID tid, int int_num, int index)
 239     {
 240         interrupts[tid]->clear(int_num, index);
 241     }
 242
 243     void
 244     clearInterrupts(ThreadID tid)
 245     {
 246         interrupts[tid]->clearAll();
 247     }
 248
 249     bool
 250     checkInterrupts(ThreadID tid) const
 251     {
 252         return FullSystem && interrupts[tid]->checkInterrupts();
 253     }
 254
 255   protected:
 256     std::vector<ThreadContext *> threadContexts;
 257
 258     Trace::InstTracer * tracer;
 259
 260   public:
 261
 262
 263     /** Invalid or unknown Pid. Possible when operating system is not present
 264      *  or has not assigned a pid yet */
 265     static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
 266
 267     // Mask to align PCs to MachInst sized boundaries
 268     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 269
 270     /// Provide access to the tracer pointer
 271     Trace::InstTracer * getTracer() { return tracer; }
 272
 273     /// Notify the CPU that the indicated context is now active.
 274     virtual void activateContext(ThreadID thread_num);
 275
 276     /// Notify the CPU that the indicated context is now suspended.
 277     /// Check if possible to enter a lower power state
 278     virtual void suspendContext(ThreadID thread_num);
 279
 280     /// Notify the CPU that the indicated context is now halted.
 281     virtual void haltContext(ThreadID thread_num);
 282
 283    /// Given a Thread Context pointer return the thread num
 284    int findContext(ThreadContext *tc);
 285
 286    /// Given a thread num get tho thread context for it
 287    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 288
 289    /// Get the number of thread contexts available
 290    unsigned numContexts() {
 291        return static_cast<unsigned>(threadContexts.size());
 292    }
 293
 294     /// Convert ContextID to threadID
 295     ThreadID contextToThread(ContextID cid)
 296     { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
 297
 298   public:
 299     typedef BaseCPUParams Params;
 300     const Params *params() const
 301     { return reinterpret_cast<const Params *>(_params); }
 302     BaseCPU(Params *params, bool is_checker = false);
 303     virtual ~BaseCPU();
 304
 305     void init() override;
 306     void startup() override;
 307     void regStats() override;
 308
 309     void regProbePoints() override;
 310
 311     void registerThreadContexts();
 312
 313     // Functions to deschedule and reschedule the events to enter the
 314     // power gating sleep before and after checkpoiting respectively.
 315     void deschedulePowerGatingEvent();
 316     void schedulePowerGatingEvent();
 317
 318     /**
 319      * Prepare for another CPU to take over execution.
 320      *
 321      * When this method exits, all internal state should have been
 322      * flushed. After the method returns, the simulator calls
 323      * takeOverFrom() on the new CPU with this CPU as its parameter.
 324      */
 325     virtual void switchOut();
 326
 327     /**
 328      * Load the state of a CPU from the previous CPU object, invoked
 329      * on all new CPUs that are about to be switched in.
 330      *
 331      * A CPU model implementing this method is expected to initialize
 332      * its state from the old CPU and connect its memory (unless they
 333      * are already connected) to the memories connected to the old
 334      * CPU.
 335      *
 336      * @param cpu CPU to initialize read state from.
 337      */
 338     virtual void takeOverFrom(BaseCPU *cpu);
 339
 340     /**
 341      * Flush all TLBs in the CPU.
 342      *
 343      * This method is mainly used to flush stale translations when
 344      * switching CPUs. It is also exported to the Python world to
 345      * allow it to request a TLB flush after draining the CPU to make
 346      * it easier to compare traces when debugging
 347      * handover/checkpointing.
 348      */
 349     void flushTLBs();
 350
 351     /**
 352      * Determine if the CPU is switched out.
 353      *
 354      * @return True if the CPU is switched out, false otherwise.
 355      */
 356     bool switchedOut() const { return _switchedOut; }
 357
 358     /**
 359      * Verify that the system is in a memory mode supported by the
 360      * CPU.
 361      *
 362      * Implementations are expected to query the system for the
 363      * current memory mode and ensure that it is what the CPU model
 364      * expects. If the check fails, the implementation should
 365      * terminate the simulation using fatal().
 366      */
 367     virtual void verifyMemoryMode() const { };
 368
 369     /**
 370      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 371      * This is a constant for the duration of the simulation.
 372      */
 373     ThreadID numThreads;
 374
 375     System *system;
 376
 377     /**
 378      * Get the cache line size of the system.
 379      */
 380     inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 381
 382     /**
 383      * Serialize this object to the given output stream.
 384      *
 385      * @note CPU models should normally overload the serializeThread()
 386      * method instead of the serialize() method as this provides a
 387      * uniform data format for all CPU models and promotes better code
 388      * reuse.
 389      *
 390      * @param cp The stream to serialize to.
 391      */
 392     void serialize(CheckpointOut &cp) const override;
 393
 394     /**
 395      * Reconstruct the state of this object from a checkpoint.
 396      *
 397      * @note CPU models should normally overload the
 398      * unserializeThread() method instead of the unserialize() method
 399      * as this provides a uniform data format for all CPU models and
 400      * promotes better code reuse.
 401
 402      * @param cp The checkpoint use.
 403      */
 404     void unserialize(CheckpointIn &cp) override;
 405
 406     /**
 407      * Serialize a single thread.
 408      *
 409      * @param cp The stream to serialize to.
 410      * @param tid ID of the current thread.
 411      */
 412     virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
 413
 414     /**
 415      * Unserialize one thread.
 416      *
 417      * @param cp The checkpoint use.
 418      * @param tid ID of the current thread.
 419      */
 420     virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
 421
 422     virtual Counter totalInsts() const = 0;
 423
 424     virtual Counter totalOps() const = 0;
 425
 426     /**
 427      * Schedule an event that exits the simulation loops after a
 428      * predefined number of instructions.
 429      *
 430      * This method is usually called from the configuration script to
 431      * get an exit event some time in the future. It is typically used
 432      * when the script wants to simulate for a specific number of
 433      * instructions rather than ticks.
 434      *
 435      * @param tid Thread monitor.
 436      * @param insts Number of instructions into the future.
 437      * @param cause Cause to signal in the exit event.
 438      */
 439     void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 440
 441     /**
 442      * Get the number of instructions executed by the specified thread
 443      * on this CPU. Used by Python to control simulation.
 444      *
 445      * @param tid Thread monitor
 446      * @return Number of instructions executed
 447      */
 448     uint64_t getCurrentInstCount(ThreadID tid);
 449
 450   public:
 451     /**
 452      * @{
 453      * @name PMU Probe points.
 454      */
 455
 456     /**
 457      * Helper method to trigger PMU probes for a committed
 458      * instruction.
 459      *
 460      * @param inst Instruction that just committed
 461      * @param pc PC of the instruction that just committed
 462      */
 463     virtual void probeInstCommit(const StaticInstPtr &inst, Addr pc);
 464
 465    protected:
 466     /**
 467      * Helper method to instantiate probe points belonging to this
 468      * object.
 469      *
 470      * @param name Name of the probe point.
 471      * @return A unique_ptr to the new probe point.
 472      */
 473     ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 474
 475     /**
 476      * Instruction commit probe point.
 477      *
 478      * This probe point is triggered whenever one or more instructions
 479      * are committed. It is normally triggered once for every
 480      * instruction. However, CPU models committing bundles of
 481      * instructions may call notify once for the entire bundle.
 482      */
 483     ProbePoints::PMUUPtr ppRetiredInsts;
 484     ProbePoints::PMUUPtr ppRetiredInstsPC;
 485
 486     /** Retired load instructions */
 487     ProbePoints::PMUUPtr ppRetiredLoads;
 488     /** Retired store instructions */
 489     ProbePoints::PMUUPtr ppRetiredStores;
 490
 491     /** Retired branches (any type) */
 492     ProbePoints::PMUUPtr ppRetiredBranches;
 493
 494     /** CPU cycle counter even if any thread Context is suspended*/
 495     ProbePoints::PMUUPtr ppAllCycles;
 496
 497     /** CPU cycle counter, only counts if any thread contexts is active **/
 498     ProbePoints::PMUUPtr ppActiveCycles;
 499
 500     /**
 501      * ProbePoint that signals transitions of threadContexts sets.
 502      * The ProbePoint reports information through it bool parameter.
 503      * - If the parameter is true then the last enabled threadContext of the
 504      * CPU object was disabled.
 505      * - If the parameter is false then a threadContext was enabled, all the
 506      * remaining threadContexts are disabled.
 507      */
 508     ProbePointArg<bool> *ppSleeping;
 509     /** @} */
 510
 511     enum CPUState {
 512         CPU_STATE_ON,
 513         CPU_STATE_SLEEP,
 514         CPU_STATE_WAKEUP
 515     };
 516
 517     Cycles previousCycle;
 518     CPUState previousState;
 519
 520     /** base method keeping track of cycle progression **/
 521     inline void updateCycleCounters(CPUState state)
 522     {
 523         uint32_t delta = curCycle() - previousCycle;
 524
 525         if (previousState == CPU_STATE_ON) {
 526             ppActiveCycles->notify(delta);
 527         }
 528
 529         switch (state)
 530         {
 531           case CPU_STATE_WAKEUP:
 532             ppSleeping->notify(false);
 533             break;
 534           case CPU_STATE_SLEEP:
 535             ppSleeping->notify(true);
 536             break;
 537           default:
 538             break;
 539         }
 540
 541         ppAllCycles->notify(delta);
 542
 543         previousCycle = curCycle();
 544         previousState = state;
 545     }
 546
 547     // Function tracing
 548   private:
 549     bool functionTracingEnabled;
 550     std::ostream *functionTraceStream;
 551     Addr currentFunctionStart;
 552     Addr currentFunctionEnd;
 553     Tick functionEntryTick;
 554     void enableFunctionTrace();
 555     void traceFunctionsInternal(Addr pc);
 556
 557   private:
 558     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 559
 560   public:
 561     void traceFunctions(Addr pc)
 562     {
 563         if (functionTracingEnabled)
 564             traceFunctionsInternal(pc);
 565     }
 566
 567     static int numSimulatedCPUs() { return cpuList.size(); }
 568     static Counter numSimulatedInsts()
 569     {
 570         Counter total = 0;
 571
 572         int size = cpuList.size();
 573         for (int i = 0; i < size; ++i)
 574             total += cpuList[i]->totalInsts();
 575
 576         return total;
 577     }
 578
 579     static Counter numSimulatedOps()
 580     {
 581         Counter total = 0;
 582
 583         int size = cpuList.size();
 584         for (int i = 0; i < size; ++i)
 585             total += cpuList[i]->totalOps();
 586
 587         return total;
 588     }
 589
 590   public:
 591     // Number of CPU cycles simulated
 592     Stats::Scalar numCycles;
 593     Stats::Scalar numWorkItemsStarted;
 594     Stats::Scalar numWorkItemsCompleted;
 595
 596   private:
 597     std::vector<AddressMonitor> addressMonitor;
 598
 599   public:
 600     void armMonitor(ThreadID tid, Addr address);
 601     bool mwait(ThreadID tid, PacketPtr pkt);
 602     void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
 603     AddressMonitor *getCpuAddrMonitor(ThreadID tid)
 604     {
 605         assert(tid < numThreads);
 606         return &addressMonitor[tid];
 607     }
 608
 609     bool waitForRemoteGDB() const;
 610
 611     Cycles syscallRetryLatency;
 612
 613   // Enables CPU to enter power gating on a configurable cycle count
 614   protected:
 615     void enterPwrGating();
 616
 617     const Cycles pwrGatingLatency;
 618     const bool powerGatingOnIdle;
 619     EventFunctionWrapper enterPwrGatingEvent;
 620 };
 621
 622 #endif // THE_ISA == NULL_ISA
 623
 624 #endif // __CPU_BASE_HH__