src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011-2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Nathan Binkert
  43  *          Rick Strong
  44  */
  45
  46 #ifndef __CPU_BASE_HH__
  47 #define __CPU_BASE_HH__
  48
  49 #include <vector>
  50
  51 // Before we do anything else, check if this build is the NULL ISA,
  52 // and if so stop here
  53 #include "config/the_isa.hh"
  54 #if THE_ISA == NULL_ISA
  55 #include "arch/null/cpu_dummy.hh"
  56 #else
  57 #include "arch/interrupts.hh"
  58 #include "arch/isa_traits.hh"
  59 #include "arch/microcode_rom.hh"
  60 #include "base/statistics.hh"
  61 #include "mem/mem_object.hh"
  62 #include "sim/eventq.hh"
  63 #include "sim/full_system.hh"
  64 #include "sim/insttracer.hh"
  65 #include "sim/probe/pmu.hh"
  66 #include "sim/system.hh"
  67 #include "debug/Mwait.hh"
  68
  69 class BaseCPU;
  70 struct BaseCPUParams;
  71 class CheckerCPU;
  72 class ThreadContext;
  73
  74 struct AddressMonitor
  75 {
  76     AddressMonitor();
  77     bool doMonitor(PacketPtr pkt);
  78
  79     bool armed;
  80     Addr vAddr;
  81     Addr pAddr;
  82     uint64_t val;
  83     bool waiting;   // 0=normal, 1=mwaiting
  84     bool gotWakeup;
  85 };
  86
  87 class CPUProgressEvent : public Event
  88 {
  89   protected:
  90     Tick _interval;
  91     Counter lastNumInst;
  92     BaseCPU *cpu;
  93     bool _repeatEvent;
  94
  95   public:
  96     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  97
  98     void process();
  99
 100     void interval(Tick ival) { _interval = ival; }
 101     Tick interval() { return _interval; }
 102
 103     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
 104
 105     virtual const char *description() const;
 106 };
 107
 108 class BaseCPU : public MemObject
 109 {
 110   protected:
 111
 112     /// Instruction count used for SPARC misc register
 113     /// @todo unify this with the counters that cpus individually keep
 114     Tick instCnt;
 115
 116     // every cpu has an id, put it in the base cpu
 117     // Set at initialization, only time a cpuId might change is during a
 118     // takeover (which should be done from within the BaseCPU anyway,
 119     // therefore no setCpuId() method is provided
 120     int _cpuId;
 121
 122     /** Each cpu will have a socket ID that corresponds to its physical location
 123      * in the system. This is usually used to bucket cpu cores under single DVFS
 124      * domain. This information may also be required by the OS to identify the
 125      * cpu core grouping (as in the case of ARM via MPIDR register)
 126      */
 127     const uint32_t _socketId;
 128
 129     /** instruction side request id that must be placed in all requests */
 130     MasterID _instMasterId;
 131
 132     /** data side request id that must be placed in all requests */
 133     MasterID _dataMasterId;
 134
 135     /** An intrenal representation of a task identifier within gem5. This is
 136      * used so the CPU can add which taskId (which is an internal representation
 137      * of the OS process ID) to each request so components in the memory system
 138      * can track which process IDs are ultimately interacting with them
 139      */
 140     uint32_t _taskId;
 141
 142     /** The current OS process ID that is executing on this processor. This is
 143      * used to generate a taskId */
 144     uint32_t _pid;
 145
 146     /** Is the CPU switched out or active? */
 147     bool _switchedOut;
 148
 149     /** Cache the cache line size that we get from the system */
 150     const unsigned int _cacheLineSize;
 151
 152   public:
 153
 154     /**
 155      * Purely virtual method that returns a reference to the data
 156      * port. All subclasses must implement this method.
 157      *
 158      * @return a reference to the data port
 159      */
 160     virtual MasterPort &getDataPort() = 0;
 161
 162     /**
 163      * Purely virtual method that returns a reference to the instruction
 164      * port. All subclasses must implement this method.
 165      *
 166      * @return a reference to the instruction port
 167      */
 168     virtual MasterPort &getInstPort() = 0;
 169
 170     /** Reads this CPU's ID. */
 171     int cpuId() const { return _cpuId; }
 172
 173     /** Reads this CPU's Socket ID. */
 174     uint32_t socketId() const { return _socketId; }
 175
 176     /** Reads this CPU's unique data requestor ID */
 177     MasterID dataMasterId() { return _dataMasterId; }
 178     /** Reads this CPU's unique instruction requestor ID */
 179     MasterID instMasterId() { return _instMasterId; }
 180
 181     /**
 182      * Get a master port on this CPU. All CPUs have a data and
 183      * instruction port, and this method uses getDataPort and
 184      * getInstPort of the subclasses to resolve the two ports.
 185      *
 186      * @param if_name the port name
 187      * @param idx ignored index
 188      *
 189      * @return a reference to the port with the given name
 190      */
 191     BaseMasterPort &getMasterPort(const std::string &if_name,
 192                                   PortID idx = InvalidPortID);
 193
 194     /** Get cpu task id */
 195     uint32_t taskId() const { return _taskId; }
 196     /** Set cpu task id */
 197     void taskId(uint32_t id) { _taskId = id; }
 198
 199     uint32_t getPid() const { return _pid; }
 200     void setPid(uint32_t pid) { _pid = pid; }
 201
 202     inline void workItemBegin() { numWorkItemsStarted++; }
 203     inline void workItemEnd() { numWorkItemsCompleted++; }
 204     // @todo remove me after debugging with legion done
 205     Tick instCount() { return instCnt; }
 206
 207     TheISA::MicrocodeRom microcodeRom;
 208
 209   protected:
 210     TheISA::Interrupts *interrupts;
 211
 212   public:
 213     TheISA::Interrupts *
 214     getInterruptController()
 215     {
 216         return interrupts;
 217     }
 218
 219     virtual void wakeup() = 0;
 220
 221     void
 222     postInterrupt(int int_num, int index)
 223     {
 224         interrupts->post(int_num, index);
 225         if (FullSystem)
 226             wakeup();
 227     }
 228
 229     void
 230     clearInterrupt(int int_num, int index)
 231     {
 232         interrupts->clear(int_num, index);
 233     }
 234
 235     void
 236     clearInterrupts()
 237     {
 238         interrupts->clearAll();
 239     }
 240
 241     bool
 242     checkInterrupts(ThreadContext *tc) const
 243     {
 244         return FullSystem && interrupts->checkInterrupts(tc);
 245     }
 246
 247     class ProfileEvent : public Event
 248     {
 249       private:
 250         BaseCPU *cpu;
 251         Tick interval;
 252
 253       public:
 254         ProfileEvent(BaseCPU *cpu, Tick interval);
 255         void process();
 256     };
 257     ProfileEvent *profileEvent;
 258
 259   protected:
 260     std::vector<ThreadContext *> threadContexts;
 261
 262     Trace::InstTracer * tracer;
 263
 264   public:
 265
 266     // Mask to align PCs to MachInst sized boundaries
 267     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 268
 269     /// Provide access to the tracer pointer
 270     Trace::InstTracer * getTracer() { return tracer; }
 271
 272     /// Notify the CPU that the indicated context is now active.
 273     virtual void activateContext(ThreadID thread_num) {}
 274
 275     /// Notify the CPU that the indicated context is now suspended.
 276     virtual void suspendContext(ThreadID thread_num) {}
 277
 278     /// Notify the CPU that the indicated context is now halted.
 279     virtual void haltContext(ThreadID thread_num) {}
 280
 281    /// Given a Thread Context pointer return the thread num
 282    int findContext(ThreadContext *tc);
 283
 284    /// Given a thread num get tho thread context for it
 285    virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 286
 287    /// Get the number of thread contexts available
 288    unsigned numContexts() { return threadContexts.size(); }
 289
 290   public:
 291     typedef BaseCPUParams Params;
 292     const Params *params() const
 293     { return reinterpret_cast<const Params *>(_params); }
 294     BaseCPU(Params *params, bool is_checker = false);
 295     virtual ~BaseCPU();
 296
 297     virtual void init();
 298     virtual void startup();
 299     virtual void regStats();
 300
 301     void regProbePoints() M5_ATTR_OVERRIDE;
 302
 303     void registerThreadContexts();
 304
 305     /**
 306      * Prepare for another CPU to take over execution.
 307      *
 308      * When this method exits, all internal state should have been
 309      * flushed. After the method returns, the simulator calls
 310      * takeOverFrom() on the new CPU with this CPU as its parameter.
 311      */
 312     virtual void switchOut();
 313
 314     /**
 315      * Load the state of a CPU from the previous CPU object, invoked
 316      * on all new CPUs that are about to be switched in.
 317      *
 318      * A CPU model implementing this method is expected to initialize
 319      * its state from the old CPU and connect its memory (unless they
 320      * are already connected) to the memories connected to the old
 321      * CPU.
 322      *
 323      * @param cpu CPU to initialize read state from.
 324      */
 325     virtual void takeOverFrom(BaseCPU *cpu);
 326
 327     /**
 328      * Flush all TLBs in the CPU.
 329      *
 330      * This method is mainly used to flush stale translations when
 331      * switching CPUs. It is also exported to the Python world to
 332      * allow it to request a TLB flush after draining the CPU to make
 333      * it easier to compare traces when debugging
 334      * handover/checkpointing.
 335      */
 336     void flushTLBs();
 337
 338     /**
 339      * Determine if the CPU is switched out.
 340      *
 341      * @return True if the CPU is switched out, false otherwise.
 342      */
 343     bool switchedOut() const { return _switchedOut; }
 344
 345     /**
 346      * Verify that the system is in a memory mode supported by the
 347      * CPU.
 348      *
 349      * Implementations are expected to query the system for the
 350      * current memory mode and ensure that it is what the CPU model
 351      * expects. If the check fails, the implementation should
 352      * terminate the simulation using fatal().
 353      */
 354     virtual void verifyMemoryMode() const { };
 355
 356     /**
 357      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 358      * This is a constant for the duration of the simulation.
 359      */
 360     ThreadID numThreads;
 361
 362     /**
 363      * Vector of per-thread instruction-based event queues.  Used for
 364      * scheduling events based on number of instructions committed by
 365      * a particular thread.
 366      */
 367     EventQueue **comInstEventQueue;
 368
 369     /**
 370      * Vector of per-thread load-based event queues.  Used for
 371      * scheduling events based on number of loads committed by
 372      *a particular thread.
 373      */
 374     EventQueue **comLoadEventQueue;
 375
 376     System *system;
 377
 378     /**
 379      * Get the cache line size of the system.
 380      */
 381     inline unsigned int cacheLineSize() const { return _cacheLineSize; }
 382
 383     /**
 384      * Serialize this object to the given output stream.
 385      *
 386      * @note CPU models should normally overload the serializeThread()
 387      * method instead of the serialize() method as this provides a
 388      * uniform data format for all CPU models and promotes better code
 389      * reuse.
 390      *
 391      * @param os The stream to serialize to.
 392      */
 393     virtual void serialize(std::ostream &os);
 394
 395     /**
 396      * Reconstruct the state of this object from a checkpoint.
 397      *
 398      * @note CPU models should normally overload the
 399      * unserializeThread() method instead of the unserialize() method
 400      * as this provides a uniform data format for all CPU models and
 401      * promotes better code reuse.
 402
 403      * @param cp The checkpoint use.
 404      * @param section The section name of this object.
 405      */
 406     virtual void unserialize(Checkpoint *cp, const std::string &section);
 407
 408     /**
 409      * Serialize a single thread.
 410      *
 411      * @param os The stream to serialize to.
 412      * @param tid ID of the current thread.
 413      */
 414     virtual void serializeThread(std::ostream &os, ThreadID tid) {};
 415
 416     /**
 417      * Unserialize one thread.
 418      *
 419      * @param cp The checkpoint use.
 420      * @param section The section name of this thread.
 421      * @param tid ID of the current thread.
 422      */
 423     virtual void unserializeThread(Checkpoint *cp, const std::string &section,
 424                                    ThreadID tid) {};
 425
 426     virtual Counter totalInsts() const = 0;
 427
 428     virtual Counter totalOps() const = 0;
 429
 430     /**
 431      * Schedule an event that exits the simulation loops after a
 432      * predefined number of instructions.
 433      *
 434      * This method is usually called from the configuration script to
 435      * get an exit event some time in the future. It is typically used
 436      * when the script wants to simulate for a specific number of
 437      * instructions rather than ticks.
 438      *
 439      * @param tid Thread monitor.
 440      * @param insts Number of instructions into the future.
 441      * @param cause Cause to signal in the exit event.
 442      */
 443     void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
 444
 445     /**
 446      * Schedule an event that exits the simulation loops after a
 447      * predefined number of load operations.
 448      *
 449      * This method is usually called from the configuration script to
 450      * get an exit event some time in the future. It is typically used
 451      * when the script wants to simulate for a specific number of
 452      * loads rather than ticks.
 453      *
 454      * @param tid Thread monitor.
 455      * @param loads Number of load instructions into the future.
 456      * @param cause Cause to signal in the exit event.
 457      */
 458     void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
 459
 460   public:
 461     /**
 462      * @{
 463      * @name PMU Probe points.
 464      */
 465
 466     /**
 467      * Helper method to trigger PMU probes for a committed
 468      * instruction.
 469      *
 470      * @param inst Instruction that just committed
 471      */
 472     virtual void probeInstCommit(const StaticInstPtr &inst);
 473
 474     /**
 475      * Helper method to instantiate probe points belonging to this
 476      * object.
 477      *
 478      * @param name Name of the probe point.
 479      * @return A unique_ptr to the new probe point.
 480      */
 481     ProbePoints::PMUUPtr pmuProbePoint(const char *name);
 482
 483     /** CPU cycle counter */
 484     ProbePoints::PMUUPtr ppCycles;
 485
 486     /**
 487      * Instruction commit probe point.
 488      *
 489      * This probe point is triggered whenever one or more instructions
 490      * are committed. It is normally triggered once for every
 491      * instruction. However, CPU models committing bundles of
 492      * instructions may call notify once for the entire bundle.
 493      */
 494     ProbePoints::PMUUPtr ppRetiredInsts;
 495
 496     /** Retired load instructions */
 497     ProbePoints::PMUUPtr ppRetiredLoads;
 498     /** Retired store instructions */
 499     ProbePoints::PMUUPtr ppRetiredStores;
 500
 501     /** Retired branches (any type) */
 502     ProbePoints::PMUUPtr ppRetiredBranches;
 503
 504     /** @} */
 505
 506
 507
 508     // Function tracing
 509   private:
 510     bool functionTracingEnabled;
 511     std::ostream *functionTraceStream;
 512     Addr currentFunctionStart;
 513     Addr currentFunctionEnd;
 514     Tick functionEntryTick;
 515     void enableFunctionTrace();
 516     void traceFunctionsInternal(Addr pc);
 517
 518   private:
 519     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 520
 521   public:
 522     void traceFunctions(Addr pc)
 523     {
 524         if (functionTracingEnabled)
 525             traceFunctionsInternal(pc);
 526     }
 527
 528     static int numSimulatedCPUs() { return cpuList.size(); }
 529     static Counter numSimulatedInsts()
 530     {
 531         Counter total = 0;
 532
 533         int size = cpuList.size();
 534         for (int i = 0; i < size; ++i)
 535             total += cpuList[i]->totalInsts();
 536
 537         return total;
 538     }
 539
 540     static Counter numSimulatedOps()
 541     {
 542         Counter total = 0;
 543
 544         int size = cpuList.size();
 545         for (int i = 0; i < size; ++i)
 546             total += cpuList[i]->totalOps();
 547
 548         return total;
 549     }
 550
 551   public:
 552     // Number of CPU cycles simulated
 553     Stats::Scalar numCycles;
 554     Stats::Scalar numWorkItemsStarted;
 555     Stats::Scalar numWorkItemsCompleted;
 556
 557   private:
 558     AddressMonitor addressMonitor;
 559
 560   public:
 561     void armMonitor(Addr address);
 562     bool mwait(PacketPtr pkt);
 563     void mwaitAtomic(ThreadContext *tc, TheISA::TLB *dtb);
 564     AddressMonitor *getCpuAddrMonitor() { return &addressMonitor; }
 565     void atomicNotify(Addr address);
 566 };
 567
 568 #endif // THE_ISA == NULL_ISA
 569
 570 #endif // __CPU_BASE_HH__