2 * Copyright (c) 2011-2013, 2017 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
46 #ifndef __CPU_BASE_HH__
47 #define __CPU_BASE_HH__
51 // Before we do anything else, check if this build is the NULL ISA,
52 // and if so stop here
53 #include "config/the_isa.hh"
54 #if THE_ISA == NULL_ISA
55 #include "arch/null/cpu_dummy.hh"
57 #include "arch/interrupts.hh"
58 #include "arch/isa_traits.hh"
59 #include "arch/microcode_rom.hh"
60 #include "base/statistics.hh"
61 #include "mem/mem_object.hh"
62 #include "sim/eventq.hh"
63 #include "sim/full_system.hh"
64 #include "sim/insttracer.hh"
65 #include "sim/probe/pmu.hh"
66 #include "sim/probe/probe.hh"
67 #include "sim/system.hh"
68 #include "debug/Mwait.hh"
78 bool doMonitor(PacketPtr pkt);
84 bool waiting; // 0=normal, 1=mwaiting
88 class CPUProgressEvent : public Event
97 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
101 void interval(Tick ival) { _interval = ival; }
102 Tick interval() { return _interval; }
104 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
106 virtual const char *description() const;
109 class BaseCPU : public MemObject
113 /// Instruction count used for SPARC misc register
114 /// @todo unify this with the counters that cpus individually keep
117 // every cpu has an id, put it in the base cpu
118 // Set at initialization, only time a cpuId might change is during a
119 // takeover (which should be done from within the BaseCPU anyway,
120 // therefore no setCpuId() method is provided
123 /** Each cpu will have a socket ID that corresponds to its physical location
124 * in the system. This is usually used to bucket cpu cores under single DVFS
125 * domain. This information may also be required by the OS to identify the
126 * cpu core grouping (as in the case of ARM via MPIDR register)
128 const uint32_t _socketId;
130 /** instruction side request id that must be placed in all requests */
131 MasterID _instMasterId;
133 /** data side request id that must be placed in all requests */
134 MasterID _dataMasterId;
136 /** An intrenal representation of a task identifier within gem5. This is
137 * used so the CPU can add which taskId (which is an internal representation
138 * of the OS process ID) to each request so components in the memory system
139 * can track which process IDs are ultimately interacting with them
143 /** The current OS process ID that is executing on this processor. This is
144 * used to generate a taskId */
147 /** Is the CPU switched out or active? */
150 /** Cache the cache line size that we get from the system */
151 const unsigned int _cacheLineSize;
156 * Purely virtual method that returns a reference to the data
157 * port. All subclasses must implement this method.
159 * @return a reference to the data port
161 virtual MasterPort &getDataPort() = 0;
164 * Purely virtual method that returns a reference to the instruction
165 * port. All subclasses must implement this method.
167 * @return a reference to the instruction port
169 virtual MasterPort &getInstPort() = 0;
171 /** Reads this CPU's ID. */
172 int cpuId() const { return _cpuId; }
174 /** Reads this CPU's Socket ID. */
175 uint32_t socketId() const { return _socketId; }
177 /** Reads this CPU's unique data requestor ID */
178 MasterID dataMasterId() { return _dataMasterId; }
179 /** Reads this CPU's unique instruction requestor ID */
180 MasterID instMasterId() { return _instMasterId; }
183 * Get a master port on this CPU. All CPUs have a data and
184 * instruction port, and this method uses getDataPort and
185 * getInstPort of the subclasses to resolve the two ports.
187 * @param if_name the port name
188 * @param idx ignored index
190 * @return a reference to the port with the given name
192 BaseMasterPort &getMasterPort(const std::string &if_name,
193 PortID idx = InvalidPortID) override;
195 /** Get cpu task id */
196 uint32_t taskId() const { return _taskId; }
197 /** Set cpu task id */
198 void taskId(uint32_t id) { _taskId = id; }
200 uint32_t getPid() const { return _pid; }
201 void setPid(uint32_t pid) { _pid = pid; }
203 inline void workItemBegin() { numWorkItemsStarted++; }
204 inline void workItemEnd() { numWorkItemsCompleted++; }
205 // @todo remove me after debugging with legion done
206 Tick instCount() { return instCnt; }
208 TheISA::MicrocodeRom microcodeRom;
211 std::vector<TheISA::Interrupts*> interrupts;
215 getInterruptController(ThreadID tid)
217 if (interrupts.empty())
220 assert(interrupts.size() > tid);
221 return interrupts[tid];
224 virtual void wakeup(ThreadID tid) = 0;
227 postInterrupt(ThreadID tid, int int_num, int index)
229 interrupts[tid]->post(int_num, index);
235 clearInterrupt(ThreadID tid, int int_num, int index)
237 interrupts[tid]->clear(int_num, index);
241 clearInterrupts(ThreadID tid)
243 interrupts[tid]->clearAll();
247 checkInterrupts(ThreadContext *tc) const
249 return FullSystem && interrupts[tc->threadId()]->checkInterrupts(tc);
252 void processProfileEvent();
253 EventFunctionWrapper * profileEvent;
256 std::vector<ThreadContext *> threadContexts;
258 Trace::InstTracer * tracer;
263 /** Invalid or unknown Pid. Possible when operating system is not present
264 * or has not assigned a pid yet */
265 static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
267 // Mask to align PCs to MachInst sized boundaries
268 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
270 /// Provide access to the tracer pointer
271 Trace::InstTracer * getTracer() { return tracer; }
273 /// Notify the CPU that the indicated context is now active.
274 virtual void activateContext(ThreadID thread_num);
276 /// Notify the CPU that the indicated context is now suspended.
277 /// Check if possible to enter a lower power state
278 virtual void suspendContext(ThreadID thread_num);
280 /// Notify the CPU that the indicated context is now halted.
281 virtual void haltContext(ThreadID thread_num);
283 /// Given a Thread Context pointer return the thread num
284 int findContext(ThreadContext *tc);
286 /// Given a thread num get tho thread context for it
287 virtual ThreadContext *getContext(int tn) { return threadContexts[tn]; }
289 /// Get the number of thread contexts available
290 unsigned numContexts() { return threadContexts.size(); }
292 /// Convert ContextID to threadID
293 ThreadID contextToThread(ContextID cid)
294 { return static_cast<ThreadID>(cid - threadContexts[0]->contextId()); }
297 typedef BaseCPUParams Params;
298 const Params *params() const
299 { return reinterpret_cast<const Params *>(_params); }
300 BaseCPU(Params *params, bool is_checker = false);
303 void init() override;
304 void startup() override;
305 void regStats() override;
307 void regProbePoints() override;
309 void registerThreadContexts();
311 // Functions to deschedule and reschedule the events to enter the
312 // power gating sleep before and after checkpoiting respectively.
313 void deschedulePowerGatingEvent();
314 void schedulePowerGatingEvent();
317 * Prepare for another CPU to take over execution.
319 * When this method exits, all internal state should have been
320 * flushed. After the method returns, the simulator calls
321 * takeOverFrom() on the new CPU with this CPU as its parameter.
323 virtual void switchOut();
326 * Load the state of a CPU from the previous CPU object, invoked
327 * on all new CPUs that are about to be switched in.
329 * A CPU model implementing this method is expected to initialize
330 * its state from the old CPU and connect its memory (unless they
331 * are already connected) to the memories connected to the old
334 * @param cpu CPU to initialize read state from.
336 virtual void takeOverFrom(BaseCPU *cpu);
339 * Flush all TLBs in the CPU.
341 * This method is mainly used to flush stale translations when
342 * switching CPUs. It is also exported to the Python world to
343 * allow it to request a TLB flush after draining the CPU to make
344 * it easier to compare traces when debugging
345 * handover/checkpointing.
350 * Determine if the CPU is switched out.
352 * @return True if the CPU is switched out, false otherwise.
354 bool switchedOut() const { return _switchedOut; }
357 * Verify that the system is in a memory mode supported by the
360 * Implementations are expected to query the system for the
361 * current memory mode and ensure that it is what the CPU model
362 * expects. If the check fails, the implementation should
363 * terminate the simulation using fatal().
365 virtual void verifyMemoryMode() const { };
368 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
369 * This is a constant for the duration of the simulation.
374 * Vector of per-thread instruction-based event queues. Used for
375 * scheduling events based on number of instructions committed by
376 * a particular thread.
378 EventQueue **comInstEventQueue;
381 * Vector of per-thread load-based event queues. Used for
382 * scheduling events based on number of loads committed by
383 *a particular thread.
385 EventQueue **comLoadEventQueue;
390 * Get the cache line size of the system.
392 inline unsigned int cacheLineSize() const { return _cacheLineSize; }
395 * Serialize this object to the given output stream.
397 * @note CPU models should normally overload the serializeThread()
398 * method instead of the serialize() method as this provides a
399 * uniform data format for all CPU models and promotes better code
402 * @param os The stream to serialize to.
404 void serialize(CheckpointOut &cp) const override;
407 * Reconstruct the state of this object from a checkpoint.
409 * @note CPU models should normally overload the
410 * unserializeThread() method instead of the unserialize() method
411 * as this provides a uniform data format for all CPU models and
412 * promotes better code reuse.
414 * @param cp The checkpoint use.
415 * @param section The section name of this object.
417 void unserialize(CheckpointIn &cp) override;
420 * Serialize a single thread.
422 * @param os The stream to serialize to.
423 * @param tid ID of the current thread.
425 virtual void serializeThread(CheckpointOut &cp, ThreadID tid) const {};
428 * Unserialize one thread.
430 * @param cp The checkpoint use.
431 * @param section The section name of this thread.
432 * @param tid ID of the current thread.
434 virtual void unserializeThread(CheckpointIn &cp, ThreadID tid) {};
436 virtual Counter totalInsts() const = 0;
438 virtual Counter totalOps() const = 0;
441 * Schedule an event that exits the simulation loops after a
442 * predefined number of instructions.
444 * This method is usually called from the configuration script to
445 * get an exit event some time in the future. It is typically used
446 * when the script wants to simulate for a specific number of
447 * instructions rather than ticks.
449 * @param tid Thread monitor.
450 * @param insts Number of instructions into the future.
451 * @param cause Cause to signal in the exit event.
453 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
456 * Schedule an event that exits the simulation loops after a
457 * predefined number of load operations.
459 * This method is usually called from the configuration script to
460 * get an exit event some time in the future. It is typically used
461 * when the script wants to simulate for a specific number of
462 * loads rather than ticks.
464 * @param tid Thread monitor.
465 * @param loads Number of load instructions into the future.
466 * @param cause Cause to signal in the exit event.
468 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
471 * Get the number of instructions executed by the specified thread
472 * on this CPU. Used by Python to control simulation.
474 * @param tid Thread monitor
475 * @return Number of instructions executed
477 uint64_t getCurrentInstCount(ThreadID tid);
482 * @name PMU Probe points.
486 * Helper method to trigger PMU probes for a committed
489 * @param inst Instruction that just committed
491 virtual void probeInstCommit(const StaticInstPtr &inst);
495 * Helper method to instantiate probe points belonging to this
498 * @param name Name of the probe point.
499 * @return A unique_ptr to the new probe point.
501 ProbePoints::PMUUPtr pmuProbePoint(const char *name);
504 * Instruction commit probe point.
506 * This probe point is triggered whenever one or more instructions
507 * are committed. It is normally triggered once for every
508 * instruction. However, CPU models committing bundles of
509 * instructions may call notify once for the entire bundle.
511 ProbePoints::PMUUPtr ppRetiredInsts;
513 /** Retired load instructions */
514 ProbePoints::PMUUPtr ppRetiredLoads;
515 /** Retired store instructions */
516 ProbePoints::PMUUPtr ppRetiredStores;
518 /** Retired branches (any type) */
519 ProbePoints::PMUUPtr ppRetiredBranches;
521 /** CPU cycle counter even if any thread Context is suspended*/
522 ProbePoints::PMUUPtr ppAllCycles;
524 /** CPU cycle counter, only counts if any thread contexts is active **/
525 ProbePoints::PMUUPtr ppActiveCycles;
528 * ProbePoint that signals transitions of threadContexts sets.
529 * The ProbePoint reports information through it bool parameter.
530 * - If the parameter is true then the last enabled threadContext of the
531 * CPU object was disabled.
532 * - If the parameter is false then a threadContext was enabled, all the
533 * remaining threadContexts are disabled.
535 ProbePointArg<bool> *ppSleeping;
544 Cycles previousCycle;
545 CPUState previousState;
547 /** base method keeping track of cycle progression **/
548 inline void updateCycleCounters(CPUState state)
550 uint32_t delta = curCycle() - previousCycle;
552 if (previousState == CPU_STATE_ON) {
553 ppActiveCycles->notify(delta);
558 case CPU_STATE_WAKEUP:
559 ppSleeping->notify(false);
561 case CPU_STATE_SLEEP:
562 ppSleeping->notify(true);
568 ppAllCycles->notify(delta);
570 previousCycle = curCycle();
571 previousState = state;
576 bool functionTracingEnabled;
577 std::ostream *functionTraceStream;
578 Addr currentFunctionStart;
579 Addr currentFunctionEnd;
580 Tick functionEntryTick;
581 void enableFunctionTrace();
582 void traceFunctionsInternal(Addr pc);
585 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
588 void traceFunctions(Addr pc)
590 if (functionTracingEnabled)
591 traceFunctionsInternal(pc);
594 static int numSimulatedCPUs() { return cpuList.size(); }
595 static Counter numSimulatedInsts()
599 int size = cpuList.size();
600 for (int i = 0; i < size; ++i)
601 total += cpuList[i]->totalInsts();
606 static Counter numSimulatedOps()
610 int size = cpuList.size();
611 for (int i = 0; i < size; ++i)
612 total += cpuList[i]->totalOps();
618 // Number of CPU cycles simulated
619 Stats::Scalar numCycles;
620 Stats::Scalar numWorkItemsStarted;
621 Stats::Scalar numWorkItemsCompleted;
624 std::vector<AddressMonitor> addressMonitor;
627 void armMonitor(ThreadID tid, Addr address);
628 bool mwait(ThreadID tid, PacketPtr pkt);
629 void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
630 AddressMonitor *getCpuAddrMonitor(ThreadID tid)
632 assert(tid < numThreads);
633 return &addressMonitor[tid];
636 bool waitForRemoteGDB() const;
638 Cycles syscallRetryLatency;
640 // Enables CPU to enter power gating on a configurable cycle count
642 void enterPwrGating();
644 const Cycles pwrGatingLatency;
645 const bool powerGatingOnIdle;
646 EventFunctionWrapper enterPwrGatingEvent;
649 #endif // THE_ISA == NULL_ISA
651 #endif // __CPU_BASE_HH__