src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2011 Regents of the University of California
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Steve Reinhardt
  30  *          Nathan Binkert
  31  *          Rick Strong
  32  */
  33
  34 #ifndef __CPU_BASE_HH__
  35 #define __CPU_BASE_HH__
  36
  37 #include <vector>
  38
  39 #include "arch/isa_traits.hh"
  40 #include "arch/microcode_rom.hh"
  41 #include "base/statistics.hh"
  42 #include "config/full_system.hh"
  43 #include "config/the_isa.hh"
  44 #include "mem/mem_object.hh"
  45 #include "sim/eventq.hh"
  46 #include "sim/insttracer.hh"
  47
  48 #if FULL_SYSTEM
  49 #include "arch/interrupts.hh"
  50 #endif
  51
  52 class BaseCPUParams;
  53 class BranchPred;
  54 class CheckerCPU;
  55 class ThreadContext;
  56 class System;
  57 class Port;
  58
  59 namespace TheISA
  60 {
  61     class Predecoder;
  62 }
  63
  64 class CPUProgressEvent : public Event
  65 {
  66   protected:
  67     Tick _interval;
  68     Counter lastNumInst;
  69     BaseCPU *cpu;
  70     bool _repeatEvent;
  71
  72   public:
  73     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  74
  75     void process();
  76
  77     void interval(Tick ival) { _interval = ival; }
  78     Tick interval() { return _interval; }
  79
  80     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
  81
  82     virtual const char *description() const;
  83 };
  84
  85 class BaseCPU : public MemObject
  86 {
  87   protected:
  88     // CPU's clock period in terms of the number of ticks of curTime.
  89     Tick clock;
  90     // @todo remove me after debugging with legion done
  91     Tick instCnt;
  92     // every cpu has an id, put it in the base cpu
  93     // Set at initialization, only time a cpuId might change is during a
  94     // takeover (which should be done from within the BaseCPU anyway,
  95     // therefore no setCpuId() method is provided
  96     int _cpuId;
  97
  98   public:
  99     /** Reads this CPU's ID. */
 100     int cpuId() { return _cpuId; }
 101
 102 //    Tick currentTick;
 103     inline Tick frequency() const { return SimClock::Frequency / clock; }
 104     inline Tick ticks(int numCycles) const { return clock * numCycles; }
 105     inline Tick curCycle() const { return curTick() / clock; }
 106     inline Tick tickToCycles(Tick val) const { return val / clock; }
 107     inline void workItemBegin() { numWorkItemsStarted++; }
 108     inline void workItemEnd() { numWorkItemsCompleted++; }
 109     // @todo remove me after debugging with legion done
 110     Tick instCount() { return instCnt; }
 111
 112     /** The next cycle the CPU should be scheduled, given a cache
 113      * access or quiesce event returning on this cycle.  This function
 114      * may return curTick() if the CPU should run on the current cycle.
 115      */
 116     Tick nextCycle();
 117
 118     /** The next cycle the CPU should be scheduled, given a cache
 119      * access or quiesce event returning on the given Tick.  This
 120      * function may return curTick() if the CPU should run on the
 121      * current cycle.
 122      * @param begin_tick The tick that the event is completing on.
 123      */
 124     Tick nextCycle(Tick begin_tick);
 125
 126     TheISA::MicrocodeRom microcodeRom;
 127
 128 #if FULL_SYSTEM
 129   protected:
 130     TheISA::Interrupts *interrupts;
 131
 132   public:
 133     TheISA::Interrupts *
 134     getInterruptController()
 135     {
 136         return interrupts;
 137     }
 138
 139     virtual void wakeup() = 0;
 140
 141     void
 142     postInterrupt(int int_num, int index)
 143     {
 144         interrupts->post(int_num, index);
 145         wakeup();
 146     }
 147
 148     void
 149     clearInterrupt(int int_num, int index)
 150     {
 151         interrupts->clear(int_num, index);
 152     }
 153
 154     void
 155     clearInterrupts()
 156     {
 157         interrupts->clearAll();
 158     }
 159
 160     bool
 161     checkInterrupts(ThreadContext *tc) const
 162     {
 163         return interrupts->checkInterrupts(tc);
 164     }
 165
 166     class ProfileEvent : public Event
 167     {
 168       private:
 169         BaseCPU *cpu;
 170         Tick interval;
 171
 172       public:
 173         ProfileEvent(BaseCPU *cpu, Tick interval);
 174         void process();
 175     };
 176     ProfileEvent *profileEvent;
 177 #endif
 178
 179   protected:
 180     std::vector<ThreadContext *> threadContexts;
 181     std::vector<TheISA::Predecoder *> predecoders;
 182
 183     Trace::InstTracer * tracer;
 184
 185   public:
 186
 187     // Mask to align PCs to MachInst sized boundaries
 188     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 189
 190     /// Provide access to the tracer pointer
 191     Trace::InstTracer * getTracer() { return tracer; }
 192
 193     /// Notify the CPU that the indicated context is now active.  The
 194     /// delay parameter indicates the number of ticks to wait before
 195     /// executing (typically 0 or 1).
 196     virtual void activateContext(int thread_num, int delay) {}
 197
 198     /// Notify the CPU that the indicated context is now suspended.
 199     virtual void suspendContext(int thread_num) {}
 200
 201     /// Notify the CPU that the indicated context is now deallocated.
 202     virtual void deallocateContext(int thread_num) {}
 203
 204     /// Notify the CPU that the indicated context is now halted.
 205     virtual void haltContext(int thread_num) {}
 206
 207    /// Given a Thread Context pointer return the thread num
 208    int findContext(ThreadContext *tc);
 209
 210    /// Given a thread num get tho thread context for it
 211    ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 212
 213   public:
 214     typedef BaseCPUParams Params;
 215     const Params *params() const
 216     { return reinterpret_cast<const Params *>(_params); }
 217     BaseCPU(Params *params);
 218     virtual ~BaseCPU();
 219
 220     virtual void init();
 221     virtual void startup();
 222     virtual void regStats();
 223
 224     virtual void activateWhenReady(ThreadID tid) {};
 225
 226     void registerThreadContexts();
 227
 228     /// Prepare for another CPU to take over execution.  When it is
 229     /// is ready (drained pipe) it signals the sampler.
 230     virtual void switchOut();
 231
 232     /// Take over execution from the given CPU.  Used for warm-up and
 233     /// sampling.
 234     virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
 235
 236     /**
 237      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 238      * This is a constant for the duration of the simulation.
 239      */
 240     ThreadID numThreads;
 241
 242     /**
 243      * Vector of per-thread instruction-based event queues.  Used for
 244      * scheduling events based on number of instructions committed by
 245      * a particular thread.
 246      */
 247     EventQueue **comInstEventQueue;
 248
 249     /**
 250      * Vector of per-thread load-based event queues.  Used for
 251      * scheduling events based on number of loads committed by
 252      *a particular thread.
 253      */
 254     EventQueue **comLoadEventQueue;
 255
 256     System *system;
 257
 258     Tick phase;
 259
 260 #if FULL_SYSTEM
 261     /**
 262      * Serialize this object to the given output stream.
 263      * @param os The stream to serialize to.
 264      */
 265     virtual void serialize(std::ostream &os);
 266
 267     /**
 268      * Reconstruct the state of this object from a checkpoint.
 269      * @param cp The checkpoint use.
 270      * @param section The section name of this object
 271      */
 272     virtual void unserialize(Checkpoint *cp, const std::string &section);
 273
 274 #endif
 275
 276     /**
 277      * Return pointer to CPU's branch predictor (NULL if none).
 278      * @return Branch predictor pointer.
 279      */
 280     virtual BranchPred *getBranchPred() { return NULL; };
 281
 282     virtual Counter totalInstructions() const = 0;
 283
 284     // Function tracing
 285   private:
 286     bool functionTracingEnabled;
 287     std::ostream *functionTraceStream;
 288     Addr currentFunctionStart;
 289     Addr currentFunctionEnd;
 290     Tick functionEntryTick;
 291     void enableFunctionTrace();
 292     void traceFunctionsInternal(Addr pc);
 293
 294   protected:
 295     void traceFunctions(Addr pc)
 296     {
 297         if (functionTracingEnabled)
 298             traceFunctionsInternal(pc);
 299     }
 300
 301   private:
 302     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 303
 304   public:
 305     static int numSimulatedCPUs() { return cpuList.size(); }
 306     static Counter numSimulatedInstructions()
 307     {
 308         Counter total = 0;
 309
 310         int size = cpuList.size();
 311         for (int i = 0; i < size; ++i)
 312             total += cpuList[i]->totalInstructions();
 313
 314         return total;
 315     }
 316
 317   public:
 318     // Number of CPU cycles simulated
 319     Stats::Scalar numCycles;
 320     Stats::Scalar numWorkItemsStarted;
 321     Stats::Scalar numWorkItemsCompleted;
 322 };
 323
 324 #endif // __CPU_BASE_HH__