2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_BASE_HH__
33 #define __CPU_BASE_HH__
37 #include "arch/isa_traits.hh"
38 #include "arch/microcode_rom.hh"
39 #include "base/statistics.hh"
40 #include "config/full_system.hh"
41 #include "config/the_isa.hh"
42 #include "sim/eventq.hh"
43 #include "sim/insttracer.hh"
44 #include "mem/mem_object.hh"
47 #include "arch/interrupts.hh"
62 class CPUProgressEvent : public Event
71 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
75 void interval(Tick ival) { _interval = ival; }
76 Tick interval() { return _interval; }
78 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
80 virtual const char *description() const;
83 class BaseCPU : public MemObject
86 // CPU's clock period in terms of the number of ticks of curTime.
88 // @todo remove me after debugging with legion done
90 // every cpu has an id, put it in the base cpu
91 // Set at initialization, only time a cpuId might change is during a
92 // takeover (which should be done from within the BaseCPU anyway,
93 // therefore no setCpuId() method is provided
97 /** Reads this CPU's ID. */
98 int cpuId() { return _cpuId; }
101 inline Tick frequency() const { return Clock::Frequency / clock; }
102 inline Tick ticks(int numCycles) const { return clock * numCycles; }
103 inline Tick curCycle() const { return curTick / clock; }
104 inline Tick tickToCycles(Tick val) const { return val / clock; }
105 // @todo remove me after debugging with legion done
106 Tick instCount() { return instCnt; }
108 /** The next cycle the CPU should be scheduled, given a cache
109 * access or quiesce event returning on this cycle. This function
110 * may return curTick if the CPU should run on the current cycle.
114 /** The next cycle the CPU should be scheduled, given a cache
115 * access or quiesce event returning on the given Tick. This
116 * function may return curTick if the CPU should run on the
118 * @param begin_tick The tick that the event is completing on.
120 Tick nextCycle(Tick begin_tick);
122 TheISA::MicrocodeRom microcodeRom;
126 TheISA::Interrupts *interrupts;
130 getInterruptController()
135 virtual void wakeup() = 0;
138 postInterrupt(int int_num, int index)
140 interrupts->post(int_num, index);
145 clearInterrupt(int int_num, int index)
147 interrupts->clear(int_num, index);
153 interrupts->clearAll();
157 checkInterrupts(ThreadContext *tc) const
159 return interrupts->checkInterrupts(tc);
162 class ProfileEvent : public Event
169 ProfileEvent(BaseCPU *cpu, Tick interval);
172 ProfileEvent *profileEvent;
176 std::vector<ThreadContext *> threadContexts;
177 std::vector<TheISA::Predecoder *> predecoders;
179 Trace::InstTracer * tracer;
183 /// Provide access to the tracer pointer
184 Trace::InstTracer * getTracer() { return tracer; }
186 /// Notify the CPU that the indicated context is now active. The
187 /// delay parameter indicates the number of ticks to wait before
188 /// executing (typically 0 or 1).
189 virtual void activateContext(int thread_num, int delay) {}
191 /// Notify the CPU that the indicated context is now suspended.
192 virtual void suspendContext(int thread_num) {}
194 /// Notify the CPU that the indicated context is now deallocated.
195 virtual void deallocateContext(int thread_num) {}
197 /// Notify the CPU that the indicated context is now halted.
198 virtual void haltContext(int thread_num) {}
200 /// Given a Thread Context pointer return the thread num
201 int findContext(ThreadContext *tc);
203 /// Given a thread num get tho thread context for it
204 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
207 typedef BaseCPUParams Params;
208 const Params *params() const
209 { return reinterpret_cast<const Params *>(_params); }
210 BaseCPU(Params *params);
214 virtual void startup();
215 virtual void regStats();
217 virtual void activateWhenReady(ThreadID tid) {};
219 void registerThreadContexts();
221 /// Prepare for another CPU to take over execution. When it is
222 /// is ready (drained pipe) it signals the sampler.
223 virtual void switchOut();
225 /// Take over execution from the given CPU. Used for warm-up and
227 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
230 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
231 * This is a constant for the duration of the simulation.
235 TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
238 * Vector of per-thread instruction-based event queues. Used for
239 * scheduling events based on number of instructions committed by
240 * a particular thread.
242 EventQueue **comInstEventQueue;
245 * Vector of per-thread load-based event queues. Used for
246 * scheduling events based on number of loads committed by
247 *a particular thread.
249 EventQueue **comLoadEventQueue;
257 * Serialize this object to the given output stream.
258 * @param os The stream to serialize to.
260 virtual void serialize(std::ostream &os);
263 * Reconstruct the state of this object from a checkpoint.
264 * @param cp The checkpoint use.
265 * @param section The section name of this object
267 virtual void unserialize(Checkpoint *cp, const std::string §ion);
272 * Return pointer to CPU's branch predictor (NULL if none).
273 * @return Branch predictor pointer.
275 virtual BranchPred *getBranchPred() { return NULL; };
277 virtual Counter totalInstructions() const = 0;
281 bool functionTracingEnabled;
282 std::ostream *functionTraceStream;
283 Addr currentFunctionStart;
284 Addr currentFunctionEnd;
285 Tick functionEntryTick;
286 void enableFunctionTrace();
287 void traceFunctionsInternal(Addr pc);
290 void traceFunctions(Addr pc)
292 if (functionTracingEnabled)
293 traceFunctionsInternal(pc);
297 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
300 static int numSimulatedCPUs() { return cpuList.size(); }
301 static Counter numSimulatedInstructions()
305 int size = cpuList.size();
306 for (int i = 0; i < size; ++i)
307 total += cpuList[i]->totalInstructions();
313 // Number of CPU cycles simulated
314 Stats::Scalar numCycles;
317 #endif // __CPU_BASE_HH__