2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_BASE_HH__
33 #define __CPU_BASE_HH__
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "sim/eventq.hh"
40 #include "mem/mem_object.hh"
41 #include "arch/isa_traits.hh"
44 #include "arch/interrupts.hh"
53 class CPUProgressEvent : public Event
61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
65 virtual const char *description();
68 class BaseCPU : public MemObject
71 // CPU's clock period in terms of the number of ticks of curTime.
76 inline Tick frequency() const { return Clock::Frequency / clock; }
77 inline Tick cycles(int numCycles) const { return clock * numCycles; }
78 inline Tick curCycle() const { return curTick / clock; }
82 // uint64_t interrupts[TheISA::NumInterruptLevels];
83 // uint64_t intstatus;
84 TheISA::Interrupts interrupts;
87 virtual void post_interrupt(int int_num, int index);
88 virtual void clear_interrupt(int int_num, int index);
89 virtual void clear_interrupts();
92 bool check_interrupts(ThreadContext * tc) const
93 { return interrupts.check_interrupts(tc); }
95 class ProfileEvent : public Event
102 ProfileEvent(BaseCPU *cpu, int interval);
105 ProfileEvent *profileEvent;
109 std::vector<ThreadContext *> threadContexts;
113 /// Notify the CPU that the indicated context is now active. The
114 /// delay parameter indicates the number of ticks to wait before
115 /// executing (typically 0 or 1).
116 virtual void activateContext(int thread_num, int delay) {}
118 /// Notify the CPU that the indicated context is now suspended.
119 virtual void suspendContext(int thread_num) {}
121 /// Notify the CPU that the indicated context is now deallocated.
122 virtual void deallocateContext(int thread_num) {}
124 /// Notify the CPU that the indicated context is now halted.
125 virtual void haltContext(int thread_num) {}
132 bool deferRegistration;
133 Counter max_insts_any_thread;
134 Counter max_insts_all_threads;
135 Counter max_loads_any_thread;
136 Counter max_loads_all_threads;
139 Tick functionTraceStart;
145 Tick progress_interval;
151 const Params *params;
153 BaseCPU(Params *params);
157 virtual void startup();
158 virtual void regStats();
160 virtual void activateWhenReady(int tid) {};
162 void registerThreadContexts();
164 /// Prepare for another CPU to take over execution. When it is
165 /// is ready (drained pipe) it signals the sampler.
166 virtual void switchOut();
168 /// Take over execution from the given CPU. Used for warm-up and
170 virtual void takeOverFrom(BaseCPU *);
173 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
174 * This is a constant for the duration of the simulation.
176 int number_of_threads;
179 * Vector of per-thread instruction-based event queues. Used for
180 * scheduling events based on number of instructions committed by
181 * a particular thread.
183 EventQueue **comInstEventQueue;
186 * Vector of per-thread load-based event queues. Used for
187 * scheduling events based on number of loads committed by
188 *a particular thread.
190 EventQueue **comLoadEventQueue;
196 * Serialize this object to the given output stream.
197 * @param os The stream to serialize to.
199 virtual void serialize(std::ostream &os);
202 * Reconstruct the state of this object from a checkpoint.
203 * @param cp The checkpoint use.
204 * @param section The section name of this object
206 virtual void unserialize(Checkpoint *cp, const std::string §ion);
211 * Return pointer to CPU's branch predictor (NULL if none).
212 * @return Branch predictor pointer.
214 virtual BranchPred *getBranchPred() { return NULL; };
216 virtual Counter totalInstructions() const { return 0; }
220 bool functionTracingEnabled;
221 std::ostream *functionTraceStream;
222 Addr currentFunctionStart;
223 Addr currentFunctionEnd;
224 Tick functionEntryTick;
225 void enableFunctionTrace();
226 void traceFunctionsInternal(Addr pc);
229 void traceFunctions(Addr pc)
231 if (functionTracingEnabled)
232 traceFunctionsInternal(pc);
236 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
239 static int numSimulatedCPUs() { return cpuList.size(); }
240 static Counter numSimulatedInstructions()
244 int size = cpuList.size();
245 for (int i = 0; i < size; ++i)
246 total += cpuList[i]->totalInstructions();
252 // Number of CPU cycles simulated
253 Stats::Scalar<> numCycles;
256 #endif // __CPU_BASE_HH__