2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_BASE_HH__
33 #define __CPU_BASE_HH__
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "sim/eventq.hh"
40 #include "mem/mem_object.hh"
41 #include "arch/isa_traits.hh"
44 #include "arch/interrupts.hh"
53 class CPUProgressEvent : public Event
61 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
65 virtual const char *description();
68 class BaseCPU : public MemObject
71 // CPU's clock period in terms of the number of ticks of curTime.
76 inline Tick frequency() const { return Clock::Frequency / clock; }
77 inline Tick cycles(int numCycles) const { return clock * numCycles; }
78 inline Tick curCycle() const { return curTick / clock; }
80 /** The next cycle the CPU should be scheduled, given a cache
81 * access or quiesce event returning on this cycle. This function
82 * may return curTick if the CPU should run on the current cycle.
86 /** The next cycle the CPU should be scheduled, given a cache
87 * access or quiesce event returning on the given Tick. This
88 * function may return curTick if the CPU should run on the
90 * @param begin_tick The tick that the event is completing on.
92 Tick nextCycle(Tick begin_tick);
96 // uint64_t interrupts[TheISA::NumInterruptLevels];
97 // uint64_t intstatus;
98 TheISA::Interrupts interrupts;
101 virtual void post_interrupt(int int_num, int index);
102 virtual void clear_interrupt(int int_num, int index);
103 virtual void clear_interrupts();
104 bool checkInterrupts;
106 bool check_interrupts(ThreadContext * tc) const
107 { return interrupts.check_interrupts(tc); }
109 class ProfileEvent : public Event
116 ProfileEvent(BaseCPU *cpu, int interval);
119 ProfileEvent *profileEvent;
123 std::vector<ThreadContext *> threadContexts;
127 /// Notify the CPU that the indicated context is now active. The
128 /// delay parameter indicates the number of ticks to wait before
129 /// executing (typically 0 or 1).
130 virtual void activateContext(int thread_num, int delay) {}
132 /// Notify the CPU that the indicated context is now suspended.
133 virtual void suspendContext(int thread_num) {}
135 /// Notify the CPU that the indicated context is now deallocated.
136 virtual void deallocateContext(int thread_num) {}
138 /// Notify the CPU that the indicated context is now halted.
139 virtual void haltContext(int thread_num) {}
146 bool deferRegistration;
147 Counter max_insts_any_thread;
148 Counter max_insts_all_threads;
149 Counter max_loads_any_thread;
150 Counter max_loads_all_threads;
153 Tick functionTraceStart;
159 bool do_statistics_insts;
160 bool do_checkpoint_insts;
163 Tick progress_interval;
169 const Params *params;
171 BaseCPU(Params *params);
175 virtual void startup();
176 virtual void regStats();
178 virtual void activateWhenReady(int tid) {};
180 void registerThreadContexts();
182 /// Prepare for another CPU to take over execution. When it is
183 /// is ready (drained pipe) it signals the sampler.
184 virtual void switchOut();
186 /// Take over execution from the given CPU. Used for warm-up and
188 virtual void takeOverFrom(BaseCPU *);
191 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
192 * This is a constant for the duration of the simulation.
194 int number_of_threads;
197 * Vector of per-thread instruction-based event queues. Used for
198 * scheduling events based on number of instructions committed by
199 * a particular thread.
201 EventQueue **comInstEventQueue;
204 * Vector of per-thread load-based event queues. Used for
205 * scheduling events based on number of loads committed by
206 *a particular thread.
208 EventQueue **comLoadEventQueue;
214 * Serialize this object to the given output stream.
215 * @param os The stream to serialize to.
217 virtual void serialize(std::ostream &os);
220 * Reconstruct the state of this object from a checkpoint.
221 * @param cp The checkpoint use.
222 * @param section The section name of this object
224 virtual void unserialize(Checkpoint *cp, const std::string §ion);
229 * Return pointer to CPU's branch predictor (NULL if none).
230 * @return Branch predictor pointer.
232 virtual BranchPred *getBranchPred() { return NULL; };
234 virtual Counter totalInstructions() const { return 0; }
238 bool functionTracingEnabled;
239 std::ostream *functionTraceStream;
240 Addr currentFunctionStart;
241 Addr currentFunctionEnd;
242 Tick functionEntryTick;
243 void enableFunctionTrace();
244 void traceFunctionsInternal(Addr pc);
247 void traceFunctions(Addr pc)
249 if (functionTracingEnabled)
250 traceFunctionsInternal(pc);
254 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
257 static int numSimulatedCPUs() { return cpuList.size(); }
258 static Counter numSimulatedInstructions()
262 int size = cpuList.size();
263 for (int i = 0; i < size; ++i)
264 total += cpuList[i]->totalInstructions();
270 // Number of CPU cycles simulated
271 Stats::Scalar<> numCycles;
274 #endif // __CPU_BASE_HH__