src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_BASE_HH__
  33 #define __CPU_BASE_HH__
  34
  35 #include <vector>
  36
  37 #include "base/statistics.hh"
  38 #include "config/full_system.hh"
  39 #include "sim/eventq.hh"
  40 #include "mem/mem_object.hh"
  41 #include "arch/isa_traits.hh"
  42
  43 #if FULL_SYSTEM
  44 #include "arch/interrupts.hh"
  45 #endif
  46
  47 class BranchPred;
  48 class CheckerCPU;
  49 class ThreadContext;
  50 class System;
  51 class Port;
  52
  53 class CPUProgressEvent : public Event
  54 {
  55   protected:
  56     Tick interval;
  57     Counter lastNumInst;
  58     BaseCPU *cpu;
  59
  60   public:
  61     CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
  62
  63     void process();
  64
  65     virtual const char *description();
  66 };
  67
  68 class BaseCPU : public MemObject
  69 {
  70   protected:
  71     // CPU's clock period in terms of the number of ticks of curTime.
  72     Tick clock;
  73
  74   public:
  75 //    Tick currentTick;
  76     inline Tick frequency() const { return Clock::Frequency / clock; }
  77     inline Tick cycles(int numCycles) const { return clock * numCycles; }
  78     inline Tick curCycle() const { return curTick / clock; }
  79
  80     /** The next cycle the CPU should be scheduled, given a cache
  81      * access or quiesce event returning on this cycle.  This function
  82      * may return curTick if the CPU should run on the current cycle.
  83      */
  84     Tick nextCycle();
  85
  86     /** The next cycle the CPU should be scheduled, given a cache
  87      * access or quiesce event returning on the given Tick.  This
  88      * function may return curTick if the CPU should run on the
  89      * current cycle.
  90      * @param begin_tick The tick that the event is completing on.
  91      */
  92     Tick nextCycle(Tick begin_tick);
  93
  94 #if FULL_SYSTEM
  95   protected:
  96 //    uint64_t interrupts[TheISA::NumInterruptLevels];
  97 //    uint64_t intstatus;
  98     TheISA::Interrupts interrupts;
  99
 100   public:
 101     virtual void post_interrupt(int int_num, int index);
 102     virtual void clear_interrupt(int int_num, int index);
 103     virtual void clear_interrupts();
 104     bool checkInterrupts;
 105
 106     bool check_interrupts(ThreadContext * tc) const
 107     { return interrupts.check_interrupts(tc); }
 108
 109     class ProfileEvent : public Event
 110     {
 111       private:
 112         BaseCPU *cpu;
 113         int interval;
 114
 115       public:
 116         ProfileEvent(BaseCPU *cpu, int interval);
 117         void process();
 118     };
 119     ProfileEvent *profileEvent;
 120 #endif
 121
 122   protected:
 123     std::vector<ThreadContext *> threadContexts;
 124
 125   public:
 126
 127     /// Notify the CPU that the indicated context is now active.  The
 128     /// delay parameter indicates the number of ticks to wait before
 129     /// executing (typically 0 or 1).
 130     virtual void activateContext(int thread_num, int delay) {}
 131
 132     /// Notify the CPU that the indicated context is now suspended.
 133     virtual void suspendContext(int thread_num) {}
 134
 135     /// Notify the CPU that the indicated context is now deallocated.
 136     virtual void deallocateContext(int thread_num) {}
 137
 138     /// Notify the CPU that the indicated context is now halted.
 139     virtual void haltContext(int thread_num) {}
 140
 141   public:
 142     struct Params
 143     {
 144         std::string name;
 145         int numberOfThreads;
 146         bool deferRegistration;
 147         Counter max_insts_any_thread;
 148         Counter max_insts_all_threads;
 149         Counter max_loads_any_thread;
 150         Counter max_loads_all_threads;
 151         Tick clock;
 152         bool functionTrace;
 153         Tick functionTraceStart;
 154         System *system;
 155         int cpu_id;
 156 #if FULL_SYSTEM
 157         Tick profile;
 158
 159         bool do_statistics_insts;
 160         bool do_checkpoint_insts;
 161         bool do_quiesce;
 162 #endif
 163         Tick progress_interval;
 164         BaseCPU *checker;
 165
 166         Params();
 167     };
 168
 169     const Params *params;
 170
 171     BaseCPU(Params *params);
 172     virtual ~BaseCPU();
 173
 174     virtual void init();
 175     virtual void startup();
 176     virtual void regStats();
 177
 178     virtual void activateWhenReady(int tid) {};
 179
 180     void registerThreadContexts();
 181
 182     /// Prepare for another CPU to take over execution.  When it is
 183     /// is ready (drained pipe) it signals the sampler.
 184     virtual void switchOut();
 185
 186     /// Take over execution from the given CPU.  Used for warm-up and
 187     /// sampling.
 188     virtual void takeOverFrom(BaseCPU *);
 189
 190     /**
 191      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 192      * This is a constant for the duration of the simulation.
 193      */
 194     int number_of_threads;
 195
 196     /**
 197      * Vector of per-thread instruction-based event queues.  Used for
 198      * scheduling events based on number of instructions committed by
 199      * a particular thread.
 200      */
 201     EventQueue **comInstEventQueue;
 202
 203     /**
 204      * Vector of per-thread load-based event queues.  Used for
 205      * scheduling events based on number of loads committed by
 206      *a particular thread.
 207      */
 208     EventQueue **comLoadEventQueue;
 209
 210     System *system;
 211
 212 #if FULL_SYSTEM
 213     /**
 214      * Serialize this object to the given output stream.
 215      * @param os The stream to serialize to.
 216      */
 217     virtual void serialize(std::ostream &os);
 218
 219     /**
 220      * Reconstruct the state of this object from a checkpoint.
 221      * @param cp The checkpoint use.
 222      * @param section The section name of this object
 223      */
 224     virtual void unserialize(Checkpoint *cp, const std::string &section);
 225
 226 #endif
 227
 228     /**
 229      * Return pointer to CPU's branch predictor (NULL if none).
 230      * @return Branch predictor pointer.
 231      */
 232     virtual BranchPred *getBranchPred() { return NULL; };
 233
 234     virtual Counter totalInstructions() const { return 0; }
 235
 236     // Function tracing
 237   private:
 238     bool functionTracingEnabled;
 239     std::ostream *functionTraceStream;
 240     Addr currentFunctionStart;
 241     Addr currentFunctionEnd;
 242     Tick functionEntryTick;
 243     void enableFunctionTrace();
 244     void traceFunctionsInternal(Addr pc);
 245
 246   protected:
 247     void traceFunctions(Addr pc)
 248     {
 249         if (functionTracingEnabled)
 250             traceFunctionsInternal(pc);
 251     }
 252
 253   private:
 254     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 255
 256   public:
 257     static int numSimulatedCPUs() { return cpuList.size(); }
 258     static Counter numSimulatedInstructions()
 259     {
 260         Counter total = 0;
 261
 262         int size = cpuList.size();
 263         for (int i = 0; i < size; ++i)
 264             total += cpuList[i]->totalInstructions();
 265
 266         return total;
 267     }
 268
 269   public:
 270     // Number of CPU cycles simulated
 271     Stats::Scalar<> numCycles;
 272 };
 273
 274 #endif // __CPU_BASE_HH__