2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Authors: Steve Reinhardt
34 #ifndef __CPU_BASE_HH__
35 #define __CPU_BASE_HH__
39 #include "arch/isa_traits.hh"
40 #include "arch/microcode_rom.hh"
41 #include "base/statistics.hh"
42 #include "config/full_system.hh"
43 #include "config/the_isa.hh"
44 #include "mem/mem_object.hh"
45 #include "sim/eventq.hh"
46 #include "sim/insttracer.hh"
49 #include "arch/interrupts.hh"
64 class CPUProgressEvent : public Event
73 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
77 void interval(Tick ival) { _interval = ival; }
78 Tick interval() { return _interval; }
80 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
82 virtual const char *description() const;
85 class BaseCPU : public MemObject
88 // CPU's clock period in terms of the number of ticks of curTime.
90 // @todo remove me after debugging with legion done
92 // every cpu has an id, put it in the base cpu
93 // Set at initialization, only time a cpuId might change is during a
94 // takeover (which should be done from within the BaseCPU anyway,
95 // therefore no setCpuId() method is provided
99 /** Reads this CPU's ID. */
100 int cpuId() { return _cpuId; }
103 inline Tick frequency() const { return SimClock::Frequency / clock; }
104 inline Tick ticks(int numCycles) const { return clock * numCycles; }
105 inline Tick curCycle() const { return curTick() / clock; }
106 inline Tick tickToCycles(Tick val) const { return val / clock; }
107 inline void workItemBegin() { numWorkItemsStarted++; }
108 inline void workItemEnd() { numWorkItemsCompleted++; }
109 // @todo remove me after debugging with legion done
110 Tick instCount() { return instCnt; }
112 /** The next cycle the CPU should be scheduled, given a cache
113 * access or quiesce event returning on this cycle. This function
114 * may return curTick() if the CPU should run on the current cycle.
118 /** The next cycle the CPU should be scheduled, given a cache
119 * access or quiesce event returning on the given Tick. This
120 * function may return curTick() if the CPU should run on the
122 * @param begin_tick The tick that the event is completing on.
124 Tick nextCycle(Tick begin_tick);
126 TheISA::MicrocodeRom microcodeRom;
130 TheISA::Interrupts *interrupts;
134 getInterruptController()
139 virtual void wakeup() = 0;
142 postInterrupt(int int_num, int index)
144 interrupts->post(int_num, index);
149 clearInterrupt(int int_num, int index)
151 interrupts->clear(int_num, index);
157 interrupts->clearAll();
161 checkInterrupts(ThreadContext *tc) const
163 return interrupts->checkInterrupts(tc);
166 class ProfileEvent : public Event
173 ProfileEvent(BaseCPU *cpu, Tick interval);
176 ProfileEvent *profileEvent;
180 std::vector<ThreadContext *> threadContexts;
181 std::vector<TheISA::Predecoder *> predecoders;
183 Trace::InstTracer * tracer;
187 // Mask to align PCs to MachInst sized boundaries
188 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
190 /// Provide access to the tracer pointer
191 Trace::InstTracer * getTracer() { return tracer; }
193 /// Notify the CPU that the indicated context is now active. The
194 /// delay parameter indicates the number of ticks to wait before
195 /// executing (typically 0 or 1).
196 virtual void activateContext(int thread_num, int delay) {}
198 /// Notify the CPU that the indicated context is now suspended.
199 virtual void suspendContext(int thread_num) {}
201 /// Notify the CPU that the indicated context is now deallocated.
202 virtual void deallocateContext(int thread_num) {}
204 /// Notify the CPU that the indicated context is now halted.
205 virtual void haltContext(int thread_num) {}
207 /// Given a Thread Context pointer return the thread num
208 int findContext(ThreadContext *tc);
210 /// Given a thread num get tho thread context for it
211 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
214 typedef BaseCPUParams Params;
215 const Params *params() const
216 { return reinterpret_cast<const Params *>(_params); }
217 BaseCPU(Params *params);
221 virtual void startup();
222 virtual void regStats();
224 virtual void activateWhenReady(ThreadID tid) {};
226 void registerThreadContexts();
228 /// Prepare for another CPU to take over execution. When it is
229 /// is ready (drained pipe) it signals the sampler.
230 virtual void switchOut();
232 /// Take over execution from the given CPU. Used for warm-up and
234 virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
237 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
238 * This is a constant for the duration of the simulation.
243 * Vector of per-thread instruction-based event queues. Used for
244 * scheduling events based on number of instructions committed by
245 * a particular thread.
247 EventQueue **comInstEventQueue;
250 * Vector of per-thread load-based event queues. Used for
251 * scheduling events based on number of loads committed by
252 *a particular thread.
254 EventQueue **comLoadEventQueue;
262 * Serialize this object to the given output stream.
263 * @param os The stream to serialize to.
265 virtual void serialize(std::ostream &os);
268 * Reconstruct the state of this object from a checkpoint.
269 * @param cp The checkpoint use.
270 * @param section The section name of this object
272 virtual void unserialize(Checkpoint *cp, const std::string §ion);
277 * Return pointer to CPU's branch predictor (NULL if none).
278 * @return Branch predictor pointer.
280 virtual BranchPred *getBranchPred() { return NULL; };
282 virtual Counter totalInstructions() const = 0;
286 bool functionTracingEnabled;
287 std::ostream *functionTraceStream;
288 Addr currentFunctionStart;
289 Addr currentFunctionEnd;
290 Tick functionEntryTick;
291 void enableFunctionTrace();
292 void traceFunctionsInternal(Addr pc);
295 void traceFunctions(Addr pc)
297 if (functionTracingEnabled)
298 traceFunctionsInternal(pc);
302 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
305 static int numSimulatedCPUs() { return cpuList.size(); }
306 static Counter numSimulatedInstructions()
310 int size = cpuList.size();
311 for (int i = 0; i < size; ++i)
312 total += cpuList[i]->totalInstructions();
318 // Number of CPU cycles simulated
319 Stats::Scalar numCycles;
320 Stats::Scalar numWorkItemsStarted;
321 Stats::Scalar numWorkItemsCompleted;
324 #endif // __CPU_BASE_HH__