2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
46 #ifndef __CPU_BASE_HH__
47 #define __CPU_BASE_HH__
51 #include "arch/interrupts.hh"
52 #include "arch/isa_traits.hh"
53 #include "arch/microcode_rom.hh"
54 #include "base/statistics.hh"
55 #include "config/the_isa.hh"
56 #include "mem/mem_object.hh"
57 #include "sim/eventq.hh"
58 #include "sim/full_system.hh"
59 #include "sim/insttracer.hh"
73 class CPUProgressEvent : public Event
82 CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
86 void interval(Tick ival) { _interval = ival; }
87 Tick interval() { return _interval; }
89 void repeatEvent(bool repeat) { _repeatEvent = repeat; }
91 virtual const char *description() const;
94 class BaseCPU : public MemObject
97 // CPU's clock period in terms of the number of ticks of curTime.
99 // @todo remove me after debugging with legion done
101 // every cpu has an id, put it in the base cpu
102 // Set at initialization, only time a cpuId might change is during a
103 // takeover (which should be done from within the BaseCPU anyway,
104 // therefore no setCpuId() method is provided
107 /** instruction side request id that must be placed in all requests */
108 MasterID _instMasterId;
110 /** data side request id that must be placed in all requests */
111 MasterID _dataMasterId;
114 * Define a base class for the CPU ports (instruction and data)
115 * that is refined in the subclasses. This class handles the
116 * common cases, i.e. the functional accesses and the status
117 * changes and address range queries. The default behaviour for
118 * both atomic and timing access is to panic and the corresponding
119 * subclasses have to override these methods.
121 class CpuPort : public Port
126 * Create a CPU port with a name and a structural owner.
128 * @param _name port name including the owner
129 * @param _name structural owner of this port
131 CpuPort(const std::string& _name, MemObject* _owner) :
137 virtual bool recvTiming(PacketPtr pkt);
139 virtual Tick recvAtomic(PacketPtr pkt);
141 virtual void recvRetry();
143 void recvFunctional(PacketPtr pkt);
145 void recvRangeChange();
150 /** Reads this CPU's ID. */
151 int cpuId() { return _cpuId; }
153 /** Reads this CPU's unique data requestor ID */
154 MasterID dataMasterId() { return _dataMasterId; }
155 /** Reads this CPU's unique instruction requestor ID */
156 MasterID instMasterId() { return _instMasterId; }
159 inline Tick frequency() const { return SimClock::Frequency / clock; }
160 inline Tick ticks(int numCycles) const { return clock * numCycles; }
161 inline Tick curCycle() const { return curTick() / clock; }
162 inline Tick tickToCycles(Tick val) const { return val / clock; }
163 inline void workItemBegin() { numWorkItemsStarted++; }
164 inline void workItemEnd() { numWorkItemsCompleted++; }
165 // @todo remove me after debugging with legion done
166 Tick instCount() { return instCnt; }
168 /** The next cycle the CPU should be scheduled, given a cache
169 * access or quiesce event returning on this cycle. This function
170 * may return curTick() if the CPU should run on the current cycle.
174 /** The next cycle the CPU should be scheduled, given a cache
175 * access or quiesce event returning on the given Tick. This
176 * function may return curTick() if the CPU should run on the
178 * @param begin_tick The tick that the event is completing on.
180 Tick nextCycle(Tick begin_tick);
182 TheISA::MicrocodeRom microcodeRom;
185 TheISA::Interrupts *interrupts;
189 getInterruptController()
194 virtual void wakeup() = 0;
197 postInterrupt(int int_num, int index)
199 interrupts->post(int_num, index);
205 clearInterrupt(int int_num, int index)
207 interrupts->clear(int_num, index);
213 interrupts->clearAll();
217 checkInterrupts(ThreadContext *tc) const
219 return FullSystem && interrupts->checkInterrupts(tc);
222 class ProfileEvent : public Event
229 ProfileEvent(BaseCPU *cpu, Tick interval);
232 ProfileEvent *profileEvent;
235 std::vector<ThreadContext *> threadContexts;
236 std::vector<TheISA::Predecoder *> predecoders;
238 Trace::InstTracer * tracer;
242 // Mask to align PCs to MachInst sized boundaries
243 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
245 /// Provide access to the tracer pointer
246 Trace::InstTracer * getTracer() { return tracer; }
248 /// Notify the CPU that the indicated context is now active. The
249 /// delay parameter indicates the number of ticks to wait before
250 /// executing (typically 0 or 1).
251 virtual void activateContext(ThreadID thread_num, int delay) {}
253 /// Notify the CPU that the indicated context is now suspended.
254 virtual void suspendContext(ThreadID thread_num) {}
256 /// Notify the CPU that the indicated context is now deallocated.
257 virtual void deallocateContext(ThreadID thread_num) {}
259 /// Notify the CPU that the indicated context is now halted.
260 virtual void haltContext(ThreadID thread_num) {}
262 /// Given a Thread Context pointer return the thread num
263 int findContext(ThreadContext *tc);
265 /// Given a thread num get tho thread context for it
266 ThreadContext *getContext(int tn) { return threadContexts[tn]; }
269 typedef BaseCPUParams Params;
270 const Params *params() const
271 { return reinterpret_cast<const Params *>(_params); }
272 BaseCPU(Params *params);
276 virtual void startup();
277 virtual void regStats();
279 virtual void activateWhenReady(ThreadID tid) {};
281 void registerThreadContexts();
283 /// Prepare for another CPU to take over execution. When it is
284 /// is ready (drained pipe) it signals the sampler.
285 virtual void switchOut();
287 /// Take over execution from the given CPU. Used for warm-up and
289 virtual void takeOverFrom(BaseCPU *);
292 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
293 * This is a constant for the duration of the simulation.
298 * Vector of per-thread instruction-based event queues. Used for
299 * scheduling events based on number of instructions committed by
300 * a particular thread.
302 EventQueue **comInstEventQueue;
305 * Vector of per-thread load-based event queues. Used for
306 * scheduling events based on number of loads committed by
307 *a particular thread.
309 EventQueue **comLoadEventQueue;
316 * Serialize this object to the given output stream.
317 * @param os The stream to serialize to.
319 virtual void serialize(std::ostream &os);
322 * Reconstruct the state of this object from a checkpoint.
323 * @param cp The checkpoint use.
324 * @param section The section name of this object
326 virtual void unserialize(Checkpoint *cp, const std::string §ion);
329 * Return pointer to CPU's branch predictor (NULL if none).
330 * @return Branch predictor pointer.
332 virtual BranchPred *getBranchPred() { return NULL; };
334 virtual Counter totalInsts() const = 0;
336 virtual Counter totalOps() const = 0;
340 bool functionTracingEnabled;
341 std::ostream *functionTraceStream;
342 Addr currentFunctionStart;
343 Addr currentFunctionEnd;
344 Tick functionEntryTick;
345 void enableFunctionTrace();
346 void traceFunctionsInternal(Addr pc);
349 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
352 void traceFunctions(Addr pc)
354 if (functionTracingEnabled)
355 traceFunctionsInternal(pc);
358 static int numSimulatedCPUs() { return cpuList.size(); }
359 static Counter numSimulatedInsts()
363 int size = cpuList.size();
364 for (int i = 0; i < size; ++i)
365 total += cpuList[i]->totalInsts();
370 static Counter numSimulatedOps()
374 int size = cpuList.size();
375 for (int i = 0; i < size; ++i)
376 total += cpuList[i]->totalOps();
382 // Number of CPU cycles simulated
383 Stats::Scalar numCycles;
384 Stats::Scalar numWorkItemsStarted;
385 Stats::Scalar numWorkItemsCompleted;
388 #endif // __CPU_BASE_HH__