2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
32 #ifndef __CPU_BASE_HH__
33 #define __CPU_BASE_HH__
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "sim/eventq.hh"
40 #include "mem/mem_object.hh"
41 #include "arch/isa_traits.hh"
49 class CPUProgressEvent : public Event
57 CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu);
61 virtual const char *description();
64 class BaseCPU : public MemObject
67 // CPU's clock period in terms of the number of ticks of curTime.
72 inline Tick frequency() const { return Clock::Frequency / clock; }
73 inline Tick cycles(int numCycles) const { return clock * numCycles; }
74 inline Tick curCycle() const { return curTick / clock; }
78 uint64_t interrupts[TheISA::NumInterruptLevels];
82 virtual void post_interrupt(int int_num, int index);
83 virtual void clear_interrupt(int int_num, int index);
84 virtual void clear_interrupts();
87 bool check_interrupt(int int_num) const {
88 if (int_num > TheISA::NumInterruptLevels)
89 panic("int_num out of bounds\n");
91 return interrupts[int_num] != 0;
94 bool check_interrupts() const { return intstatus != 0; }
95 uint64_t intr_status() const { return intstatus; }
97 class ProfileEvent : public Event
104 ProfileEvent(BaseCPU *cpu, int interval);
107 ProfileEvent *profileEvent;
111 std::vector<ThreadContext *> threadContexts;
115 /// Notify the CPU that the indicated context is now active. The
116 /// delay parameter indicates the number of ticks to wait before
117 /// executing (typically 0 or 1).
118 virtual void activateContext(int thread_num, int delay) {}
120 /// Notify the CPU that the indicated context is now suspended.
121 virtual void suspendContext(int thread_num) {}
123 /// Notify the CPU that the indicated context is now deallocated.
124 virtual void deallocateContext(int thread_num) {}
126 /// Notify the CPU that the indicated context is now halted.
127 virtual void haltContext(int thread_num) {}
134 bool deferRegistration;
135 Counter max_insts_any_thread;
136 Counter max_insts_all_threads;
137 Counter max_loads_any_thread;
138 Counter max_loads_all_threads;
141 Tick functionTraceStart;
147 Tick progress_interval;
153 const Params *params;
155 BaseCPU(Params *params);
159 virtual void startup();
160 virtual void regStats();
162 virtual void activateWhenReady(int tid) {};
164 void registerThreadContexts();
166 /// Prepare for another CPU to take over execution. When it is
167 /// is ready (drained pipe) it signals the sampler.
168 virtual void switchOut();
170 /// Take over execution from the given CPU. Used for warm-up and
172 virtual void takeOverFrom(BaseCPU *);
175 * Number of threads we're actually simulating (<= SMT_MAX_THREADS).
176 * This is a constant for the duration of the simulation.
178 int number_of_threads;
181 * Vector of per-thread instruction-based event queues. Used for
182 * scheduling events based on number of instructions committed by
183 * a particular thread.
185 EventQueue **comInstEventQueue;
188 * Vector of per-thread load-based event queues. Used for
189 * scheduling events based on number of loads committed by
190 *a particular thread.
192 EventQueue **comLoadEventQueue;
198 * Serialize this object to the given output stream.
199 * @param os The stream to serialize to.
201 virtual void serialize(std::ostream &os);
204 * Reconstruct the state of this object from a checkpoint.
205 * @param cp The checkpoint use.
206 * @param section The section name of this object
208 virtual void unserialize(Checkpoint *cp, const std::string §ion);
213 * Return pointer to CPU's branch predictor (NULL if none).
214 * @return Branch predictor pointer.
216 virtual BranchPred *getBranchPred() { return NULL; };
218 virtual Counter totalInstructions() const { return 0; }
222 bool functionTracingEnabled;
223 std::ostream *functionTraceStream;
224 Addr currentFunctionStart;
225 Addr currentFunctionEnd;
226 Tick functionEntryTick;
227 void enableFunctionTrace();
228 void traceFunctionsInternal(Addr pc);
231 void traceFunctions(Addr pc)
233 if (functionTracingEnabled)
234 traceFunctionsInternal(pc);
238 static std::vector<BaseCPU *> cpuList; //!< Static global cpu list
241 static int numSimulatedCPUs() { return cpuList.size(); }
242 static Counter numSimulatedInstructions()
246 int size = cpuList.size();
247 for (int i = 0; i < size; ++i)
248 total += cpuList[i]->totalInstructions();
254 // Number of CPU cycles simulated
255 Stats::Scalar<> numCycles;
258 #endif // __CPU_BASE_HH__