src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Nathan Binkert
  30  */
  31
  32 #ifndef __CPU_BASE_HH__
  33 #define __CPU_BASE_HH__
  34
  35 #include <vector>
  36
  37 #include "arch/isa_traits.hh"
  38 #include "arch/microcode_rom.hh"
  39 #include "base/statistics.hh"
  40 #include "config/full_system.hh"
  41 #include "sim/eventq.hh"
  42 #include "sim/insttracer.hh"
  43 #include "mem/mem_object.hh"
  44
  45 #if FULL_SYSTEM
  46 #include "arch/interrupts.hh"
  47 #endif
  48
  49 class BaseCPUParams;
  50 class BranchPred;
  51 class CheckerCPU;
  52 class ThreadContext;
  53 class System;
  54 class Port;
  55
  56 namespace TheISA
  57 {
  58     class Predecoder;
  59 }
  60
  61 class CPUProgressEvent : public Event
  62 {
  63   protected:
  64     Tick interval;
  65     Counter lastNumInst;
  66     BaseCPU *cpu;
  67
  68   public:
  69     CPUProgressEvent(BaseCPU *_cpu, Tick ival);
  70
  71     void process();
  72
  73     virtual const char *description() const;
  74 };
  75
  76 class BaseCPU : public MemObject
  77 {
  78   protected:
  79     // CPU's clock period in terms of the number of ticks of curTime.
  80     Tick clock;
  81     // @todo remove me after debugging with legion done
  82     Tick instCnt;
  83     // every cpu has an id, put it in the base cpu
  84     // Set at initialization, only time a cpuId might change is during a
  85     // takeover (which should be done from within the BaseCPU anyway,
  86     // therefore no setCpuId() method is provided
  87     int _cpuId;
  88
  89   public:
  90     /** Reads this CPU's ID. */
  91     int cpuId() { return _cpuId; }
  92
  93 //    Tick currentTick;
  94     inline Tick frequency() const { return Clock::Frequency / clock; }
  95     inline Tick ticks(int numCycles) const { return clock * numCycles; }
  96     inline Tick curCycle() const { return curTick / clock; }
  97     inline Tick tickToCycles(Tick val) const { return val / clock; }
  98     // @todo remove me after debugging with legion done
  99     Tick instCount() { return instCnt; }
 100
 101     /** The next cycle the CPU should be scheduled, given a cache
 102      * access or quiesce event returning on this cycle.  This function
 103      * may return curTick if the CPU should run on the current cycle.
 104      */
 105     Tick nextCycle();
 106
 107     /** The next cycle the CPU should be scheduled, given a cache
 108      * access or quiesce event returning on the given Tick.  This
 109      * function may return curTick if the CPU should run on the
 110      * current cycle.
 111      * @param begin_tick The tick that the event is completing on.
 112      */
 113     Tick nextCycle(Tick begin_tick);
 114
 115     TheISA::MicrocodeRom microcodeRom;
 116
 117 #if FULL_SYSTEM
 118   protected:
 119     TheISA::Interrupts *interrupts;
 120
 121   public:
 122     TheISA::Interrupts *
 123     getInterruptController()
 124     {
 125         return interrupts;
 126     }
 127
 128     virtual void wakeup() = 0;
 129
 130     void
 131     postInterrupt(int int_num, int index)
 132     {
 133         interrupts->post(int_num, index);
 134         wakeup();
 135     }
 136
 137     void
 138     clearInterrupt(int int_num, int index)
 139     {
 140         interrupts->clear(int_num, index);
 141     }
 142
 143     void
 144     clearInterrupts()
 145     {
 146         interrupts->clearAll();
 147     }
 148
 149     bool
 150     checkInterrupts(ThreadContext *tc) const
 151     {
 152         return interrupts->checkInterrupts(tc);
 153     }
 154
 155     class ProfileEvent : public Event
 156     {
 157       private:
 158         BaseCPU *cpu;
 159         Tick interval;
 160
 161       public:
 162         ProfileEvent(BaseCPU *cpu, Tick interval);
 163         void process();
 164     };
 165     ProfileEvent *profileEvent;
 166 #endif
 167
 168   protected:
 169     std::vector<ThreadContext *> threadContexts;
 170     std::vector<TheISA::Predecoder *> predecoders;
 171
 172     Trace::InstTracer * tracer;
 173
 174   public:
 175
 176     /// Provide access to the tracer pointer
 177     Trace::InstTracer * getTracer() { return tracer; }
 178
 179     /// Notify the CPU that the indicated context is now active.  The
 180     /// delay parameter indicates the number of ticks to wait before
 181     /// executing (typically 0 or 1).
 182     virtual void activateContext(int thread_num, int delay) {}
 183
 184     /// Notify the CPU that the indicated context is now suspended.
 185     virtual void suspendContext(int thread_num) {}
 186
 187     /// Notify the CPU that the indicated context is now deallocated.
 188     virtual void deallocateContext(int thread_num) {}
 189
 190     /// Notify the CPU that the indicated context is now halted.
 191     virtual void haltContext(int thread_num) {}
 192
 193    /// Given a Thread Context pointer return the thread num
 194    int findContext(ThreadContext *tc);
 195
 196    /// Given a thread num get tho thread context for it
 197    ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 198
 199   public:
 200     typedef BaseCPUParams Params;
 201     const Params *params() const
 202     { return reinterpret_cast<const Params *>(_params); }
 203     BaseCPU(Params *params);
 204     virtual ~BaseCPU();
 205
 206     virtual void init();
 207     virtual void startup();
 208     virtual void regStats();
 209
 210     virtual void activateWhenReady(int tid) {};
 211
 212     void registerThreadContexts();
 213
 214     /// Prepare for another CPU to take over execution.  When it is
 215     /// is ready (drained pipe) it signals the sampler.
 216     virtual void switchOut();
 217
 218     /// Take over execution from the given CPU.  Used for warm-up and
 219     /// sampling.
 220     virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
 221
 222     /**
 223      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 224      * This is a constant for the duration of the simulation.
 225      */
 226     int number_of_threads;
 227
 228     TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
 229
 230     /**
 231      * Vector of per-thread instruction-based event queues.  Used for
 232      * scheduling events based on number of instructions committed by
 233      * a particular thread.
 234      */
 235     EventQueue **comInstEventQueue;
 236
 237     /**
 238      * Vector of per-thread load-based event queues.  Used for
 239      * scheduling events based on number of loads committed by
 240      *a particular thread.
 241      */
 242     EventQueue **comLoadEventQueue;
 243
 244     System *system;
 245
 246     Tick phase;
 247
 248 #if FULL_SYSTEM
 249     /**
 250      * Serialize this object to the given output stream.
 251      * @param os The stream to serialize to.
 252      */
 253     virtual void serialize(std::ostream &os);
 254
 255     /**
 256      * Reconstruct the state of this object from a checkpoint.
 257      * @param cp The checkpoint use.
 258      * @param section The section name of this object
 259      */
 260     virtual void unserialize(Checkpoint *cp, const std::string &section);
 261
 262 #endif
 263
 264     /**
 265      * Return pointer to CPU's branch predictor (NULL if none).
 266      * @return Branch predictor pointer.
 267      */
 268     virtual BranchPred *getBranchPred() { return NULL; };
 269
 270     virtual Counter totalInstructions() const { return 0; }
 271
 272     // Function tracing
 273   private:
 274     bool functionTracingEnabled;
 275     std::ostream *functionTraceStream;
 276     Addr currentFunctionStart;
 277     Addr currentFunctionEnd;
 278     Tick functionEntryTick;
 279     void enableFunctionTrace();
 280     void traceFunctionsInternal(Addr pc);
 281
 282   protected:
 283     void traceFunctions(Addr pc)
 284     {
 285         if (functionTracingEnabled)
 286             traceFunctionsInternal(pc);
 287     }
 288
 289   private:
 290     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 291
 292   public:
 293     static int numSimulatedCPUs() { return cpuList.size(); }
 294     static Counter numSimulatedInstructions()
 295     {
 296         Counter total = 0;
 297
 298         int size = cpuList.size();
 299         for (int i = 0; i < size; ++i)
 300             total += cpuList[i]->totalInstructions();
 301
 302         return total;
 303     }
 304
 305   public:
 306     // Number of CPU cycles simulated
 307     Stats::Scalar numCycles;
 308 };
 309
 310 #endif // __CPU_BASE_HH__