src/cpu/base.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * Copyright (c) 2011 Regents of the University of California
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Nathan Binkert
  43  *          Rick Strong
  44  */
  45
  46 #ifndef __CPU_BASE_HH__
  47 #define __CPU_BASE_HH__
  48
  49 #include <vector>
  50
  51 #include "arch/interrupts.hh"
  52 #include "arch/isa_traits.hh"
  53 #include "arch/microcode_rom.hh"
  54 #include "base/statistics.hh"
  55 #include "config/the_isa.hh"
  56 #include "mem/mem_object.hh"
  57 #include "sim/eventq.hh"
  58 #include "sim/full_system.hh"
  59 #include "sim/insttracer.hh"
  60
  61 struct BaseCPUParams;
  62 class BranchPred;
  63 class CheckerCPU;
  64 class ThreadContext;
  65 class System;
  66
  67 namespace TheISA
  68 {
  69     class Predecoder;
  70 }
  71
  72 class CPUProgressEvent : public Event
  73 {
  74   protected:
  75     Tick _interval;
  76     Counter lastNumInst;
  77     BaseCPU *cpu;
  78     bool _repeatEvent;
  79
  80   public:
  81     CPUProgressEvent(BaseCPU *_cpu, Tick ival = 0);
  82
  83     void process();
  84
  85     void interval(Tick ival) { _interval = ival; }
  86     Tick interval() { return _interval; }
  87
  88     void repeatEvent(bool repeat) { _repeatEvent = repeat; }
  89
  90     virtual const char *description() const;
  91 };
  92
  93 class BaseCPU : public MemObject
  94 {
  95   protected:
  96     // CPU's clock period in terms of the number of ticks of curTime.
  97     Tick clock;
  98     // @todo remove me after debugging with legion done
  99     Tick instCnt;
 100     // every cpu has an id, put it in the base cpu
 101     // Set at initialization, only time a cpuId might change is during a
 102     // takeover (which should be done from within the BaseCPU anyway,
 103     // therefore no setCpuId() method is provided
 104     int _cpuId;
 105
 106     /** instruction side request id that must be placed in all requests */
 107     MasterID _instMasterId;
 108
 109     /** data side request id that must be placed in all requests */
 110     MasterID _dataMasterId;
 111
 112     /**
 113      * Define a base class for the CPU ports (instruction and data)
 114      * that is refined in the subclasses. This class handles the
 115      * common cases, i.e. the functional accesses and the status
 116      * changes and address range queries. The default behaviour for
 117      * both atomic and timing access is to panic and the corresponding
 118      * subclasses have to override these methods.
 119      */
 120     class CpuPort : public MasterPort
 121     {
 122       public:
 123
 124         /**
 125          * Create a CPU port with a name and a structural owner.
 126          *
 127          * @param _name port name including the owner
 128          * @param _name structural owner of this port
 129          */
 130         CpuPort(const std::string& _name, MemObject* _owner) :
 131             MasterPort(_name, _owner)
 132         { }
 133
 134       protected:
 135
 136         virtual bool recvTiming(PacketPtr pkt);
 137
 138         virtual Tick recvAtomic(PacketPtr pkt);
 139
 140         virtual void recvRetry();
 141
 142         void recvFunctional(PacketPtr pkt);
 143
 144     };
 145
 146   public:
 147
 148     /**
 149      * Purely virtual method that returns a reference to the data
 150      * port. All subclasses must implement this method.
 151      *
 152      * @return a reference to the data port
 153      */
 154     virtual CpuPort &getDataPort() = 0;
 155
 156     /**
 157      * Purely virtual method that returns a reference to the instruction
 158      * port. All subclasses must implement this method.
 159      *
 160      * @return a reference to the instruction port
 161      */
 162     virtual CpuPort &getInstPort() = 0;
 163
 164     /** Reads this CPU's ID. */
 165     int cpuId() { return _cpuId; }
 166
 167     /** Reads this CPU's unique data requestor ID */
 168     MasterID dataMasterId() { return _dataMasterId; }
 169     /** Reads this CPU's unique instruction requestor ID */
 170     MasterID instMasterId() { return _instMasterId; }
 171
 172     /**
 173      * Get a master port on this MemObject. This method is virtual to allow
 174      * the subclasses of the BaseCPU to override it. All CPUs have a
 175      * data and instruction port, but the Atomic CPU (in its current
 176      * form) adds a port directly connected to the memory and has to
 177      * override getMasterPort.
 178      *
 179      * This method uses getDataPort and getInstPort to resolve the two
 180      * ports.
 181      *
 182      * @param if_name the port name
 183      * @param idx ignored index
 184      *
 185      * @return a reference to the port with the given name
 186      */
 187     virtual MasterPort &getMasterPort(const std::string &if_name,
 188                                       int idx = -1);
 189
 190 //    Tick currentTick;
 191     inline Tick frequency() const { return SimClock::Frequency / clock; }
 192     inline Tick ticks(int numCycles) const { return clock * numCycles; }
 193     inline Tick curCycle() const { return curTick() / clock; }
 194     inline Tick tickToCycles(Tick val) const { return val / clock; }
 195     inline void workItemBegin() { numWorkItemsStarted++; }
 196     inline void workItemEnd() { numWorkItemsCompleted++; }
 197     // @todo remove me after debugging with legion done
 198     Tick instCount() { return instCnt; }
 199
 200     /** The next cycle the CPU should be scheduled, given a cache
 201      * access or quiesce event returning on this cycle.  This function
 202      * may return curTick() if the CPU should run on the current cycle.
 203      */
 204     Tick nextCycle();
 205
 206     /** The next cycle the CPU should be scheduled, given a cache
 207      * access or quiesce event returning on the given Tick.  This
 208      * function may return curTick() if the CPU should run on the
 209      * current cycle.
 210      * @param begin_tick The tick that the event is completing on.
 211      */
 212     Tick nextCycle(Tick begin_tick);
 213
 214     TheISA::MicrocodeRom microcodeRom;
 215
 216   protected:
 217     TheISA::Interrupts *interrupts;
 218
 219   public:
 220     TheISA::Interrupts *
 221     getInterruptController()
 222     {
 223         return interrupts;
 224     }
 225
 226     virtual void wakeup() = 0;
 227
 228     void
 229     postInterrupt(int int_num, int index)
 230     {
 231         interrupts->post(int_num, index);
 232         if (FullSystem)
 233             wakeup();
 234     }
 235
 236     void
 237     clearInterrupt(int int_num, int index)
 238     {
 239         interrupts->clear(int_num, index);
 240     }
 241
 242     void
 243     clearInterrupts()
 244     {
 245         interrupts->clearAll();
 246     }
 247
 248     bool
 249     checkInterrupts(ThreadContext *tc) const
 250     {
 251         return FullSystem && interrupts->checkInterrupts(tc);
 252     }
 253
 254     class ProfileEvent : public Event
 255     {
 256       private:
 257         BaseCPU *cpu;
 258         Tick interval;
 259
 260       public:
 261         ProfileEvent(BaseCPU *cpu, Tick interval);
 262         void process();
 263     };
 264     ProfileEvent *profileEvent;
 265
 266   protected:
 267     std::vector<ThreadContext *> threadContexts;
 268     std::vector<TheISA::Predecoder *> predecoders;
 269
 270     Trace::InstTracer * tracer;
 271
 272   public:
 273
 274     // Mask to align PCs to MachInst sized boundaries
 275     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 276
 277     /// Provide access to the tracer pointer
 278     Trace::InstTracer * getTracer() { return tracer; }
 279
 280     /// Notify the CPU that the indicated context is now active.  The
 281     /// delay parameter indicates the number of ticks to wait before
 282     /// executing (typically 0 or 1).
 283     virtual void activateContext(ThreadID thread_num, int delay) {}
 284
 285     /// Notify the CPU that the indicated context is now suspended.
 286     virtual void suspendContext(ThreadID thread_num) {}
 287
 288     /// Notify the CPU that the indicated context is now deallocated.
 289     virtual void deallocateContext(ThreadID thread_num) {}
 290
 291     /// Notify the CPU that the indicated context is now halted.
 292     virtual void haltContext(ThreadID thread_num) {}
 293
 294    /// Given a Thread Context pointer return the thread num
 295    int findContext(ThreadContext *tc);
 296
 297    /// Given a thread num get tho thread context for it
 298    ThreadContext *getContext(int tn) { return threadContexts[tn]; }
 299
 300   public:
 301     typedef BaseCPUParams Params;
 302     const Params *params() const
 303     { return reinterpret_cast<const Params *>(_params); }
 304     BaseCPU(Params *params, bool is_checker = false);
 305     virtual ~BaseCPU();
 306
 307     virtual void init();
 308     virtual void startup();
 309     virtual void regStats();
 310
 311     virtual void activateWhenReady(ThreadID tid) {};
 312
 313     void registerThreadContexts();
 314
 315     /// Prepare for another CPU to take over execution.  When it is
 316     /// is ready (drained pipe) it signals the sampler.
 317     virtual void switchOut();
 318
 319     /// Take over execution from the given CPU.  Used for warm-up and
 320     /// sampling.
 321     virtual void takeOverFrom(BaseCPU *);
 322
 323     /**
 324      *  Number of threads we're actually simulating (<= SMT_MAX_THREADS).
 325      * This is a constant for the duration of the simulation.
 326      */
 327     ThreadID numThreads;
 328
 329     /**
 330      * Vector of per-thread instruction-based event queues.  Used for
 331      * scheduling events based on number of instructions committed by
 332      * a particular thread.
 333      */
 334     EventQueue **comInstEventQueue;
 335
 336     /**
 337      * Vector of per-thread load-based event queues.  Used for
 338      * scheduling events based on number of loads committed by
 339      *a particular thread.
 340      */
 341     EventQueue **comLoadEventQueue;
 342
 343     System *system;
 344
 345     Tick phase;
 346
 347     /**
 348      * Serialize this object to the given output stream.
 349      * @param os The stream to serialize to.
 350      */
 351     virtual void serialize(std::ostream &os);
 352
 353     /**
 354      * Reconstruct the state of this object from a checkpoint.
 355      * @param cp The checkpoint use.
 356      * @param section The section name of this object
 357      */
 358     virtual void unserialize(Checkpoint *cp, const std::string &section);
 359
 360     /**
 361      * Return pointer to CPU's branch predictor (NULL if none).
 362      * @return Branch predictor pointer.
 363      */
 364     virtual BranchPred *getBranchPred() { return NULL; };
 365
 366     virtual Counter totalInsts() const = 0;
 367
 368     virtual Counter totalOps() const = 0;
 369
 370     // Function tracing
 371   private:
 372     bool functionTracingEnabled;
 373     std::ostream *functionTraceStream;
 374     Addr currentFunctionStart;
 375     Addr currentFunctionEnd;
 376     Tick functionEntryTick;
 377     void enableFunctionTrace();
 378     void traceFunctionsInternal(Addr pc);
 379
 380   private:
 381     static std::vector<BaseCPU *> cpuList;   //!< Static global cpu list
 382
 383   public:
 384     void traceFunctions(Addr pc)
 385     {
 386         if (functionTracingEnabled)
 387             traceFunctionsInternal(pc);
 388     }
 389
 390     static int numSimulatedCPUs() { return cpuList.size(); }
 391     static Counter numSimulatedInsts()
 392     {
 393         Counter total = 0;
 394
 395         int size = cpuList.size();
 396         for (int i = 0; i < size; ++i)
 397             total += cpuList[i]->totalInsts();
 398
 399         return total;
 400     }
 401
 402     static Counter numSimulatedOps()
 403     {
 404         Counter total = 0;
 405
 406         int size = cpuList.size();
 407         for (int i = 0; i < size; ++i)
 408             total += cpuList[i]->totalOps();
 409
 410         return total;
 411     }
 412
 413   public:
 414     // Number of CPU cycles simulated
 415     Stats::Scalar numCycles;
 416     Stats::Scalar numWorkItemsStarted;
 417     Stats::Scalar numWorkItemsCompleted;
 418 };
 419
 420 #endif // __CPU_BASE_HH__