src/cpu/base_dyn_inst.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <iostream>
  32 #include <set>
  33 #include <string>
  34 #include <sstream>
  35
  36 #include "base/cprintf.hh"
  37 #include "base/trace.hh"
  38
  39 #include "arch/faults.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "mem/request.hh"
  42
  43 #include "cpu/base_dyn_inst.hh"
  44 #include "cpu/o3/alpha_impl.hh"
  45 #include "cpu/o3/alpha_cpu.hh"
  46 //#include "cpu/ozone/simple_impl.hh"
  47 //#include "cpu/ozone/ozone_impl.hh"
  48
  49 using namespace std;
  50 using namespace TheISA;
  51
  52 #define NOHASH
  53 #ifndef NOHASH
  54
  55 #include "base/hashmap.hh"
  56
  57 unsigned int MyHashFunc(const BaseDynInst *addr)
  58 {
  59     unsigned a = (unsigned)addr;
  60     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
  61
  62     return hash;
  63 }
  64
  65 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
  66 my_hash_t;
  67
  68 my_hash_t thishash;
  69 #endif
  70
  71 template <class Impl>
  72 BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
  73                                Addr pred_PC, InstSeqNum seq_num,
  74                                FullCPU *cpu)
  75   : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/
  76 {
  77     seqNum = seq_num;
  78
  79     PC = inst_PC;
  80     nextPC = PC + sizeof(MachInst);
  81     predPC = pred_PC;
  82
  83     initVars();
  84 }
  85
  86 template <class Impl>
  87 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
  88     : staticInst(_staticInst), traceData(NULL)
  89 {
  90     seqNum = 0;
  91     initVars();
  92 }
  93
  94 template <class Impl>
  95 void
  96 BaseDynInst<Impl>::initVars()
  97 {
  98     req = NULL;
  99     effAddr = 0;
 100     physEffAddr = 0;
 101     storeSize = 0;
 102
 103     readyRegs = 0;
 104
 105     completed = false;
 106     resultReady = false;
 107     canIssue = false;
 108     issued = false;
 109     executed = false;
 110     canCommit = false;
 111     committed = false;
 112     squashed = false;
 113     squashedInIQ = false;
 114     squashedInLSQ = false;
 115     squashedInROB = false;
 116     eaCalcDone = false;
 117     memOpDone = false;
 118     lqIdx = -1;
 119     sqIdx = -1;
 120     reachedCommit = false;
 121
 122     blockingInst = false;
 123     recoverInst = false;
 124
 125     iqEntry = false;
 126     robEntry = false;
 127
 128     serializeBefore = false;
 129     serializeAfter = false;
 130     serializeHandled = false;
 131
 132     // Eventually make this a parameter.
 133     threadNumber = 0;
 134
 135     // Also make this a parameter, or perhaps get it from xc or cpu.
 136     asid = 0;
 137
 138     // Initialize the fault to be unimplemented opcode.
 139 //    fault = new UnimplementedOpcodeFault;
 140     fault = NoFault;
 141
 142     ++instcount;
 143
 144     if (instcount > 1500) {
 145         cpu->dumpInsts();
 146 #ifdef DEBUG
 147         dumpSNList();
 148 #endif
 149         assert(instcount <= 1500);
 150     }
 151
 152     DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
 153             seqNum, instcount);
 154
 155 #ifdef DEBUG
 156     cpu->snList.insert(seqNum);
 157 #endif
 158 }
 159
 160 template <class Impl>
 161 BaseDynInst<Impl>::~BaseDynInst()
 162 {
 163     if (req) {
 164         req = NULL;
 165     }
 166
 167     if (traceData) {
 168         delete traceData;
 169     }
 170
 171     fault = NoFault;
 172
 173     --instcount;
 174
 175     DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
 176             seqNum, instcount);
 177 #ifdef DEBUG
 178     cpu->snList.erase(seqNum);
 179 #endif
 180 }
 181
 182 #ifdef DEBUG
 183 template <class Impl>
 184 void
 185 BaseDynInst<Impl>::dumpSNList()
 186 {
 187     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 188
 189     int count = 0;
 190     while (sn_it != cpu->snList.end()) {
 191         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 192         count++;
 193         sn_it++;
 194     }
 195 }
 196 #endif
 197
 198 template <class Impl>
 199 void
 200 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
 201 {
 202     // This is the "functional" implementation of prefetch.  Not much
 203     // happens here since prefetches don't affect the architectural
 204     // state.
 205 /*
 206     // Generate a MemReq so we can translate the effective address.
 207     MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
 208     req->asid = asid;
 209
 210     // Prefetches never cause faults.
 211     fault = NoFault;
 212
 213     // note this is a local, not BaseDynInst::fault
 214     Fault trans_fault = cpu->translateDataReadReq(req);
 215
 216     if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
 217         // It's a valid address to cacheable space.  Record key MemReq
 218         // parameters so we can generate another one just like it for
 219         // the timing access without calling translate() again (which
 220         // might mess up the TLB).
 221         effAddr = req->vaddr;
 222         physEffAddr = req->paddr;
 223         memReqFlags = req->flags;
 224     } else {
 225         // Bogus address (invalid or uncacheable space).  Mark it by
 226         // setting the eff_addr to InvalidAddr.
 227         effAddr = physEffAddr = MemReq::inval_addr;
 228     }
 229
 230     if (traceData) {
 231         traceData->setAddr(addr);
 232     }
 233 */
 234 }
 235
 236 template <class Impl>
 237 void
 238 BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 239 {
 240     // Need to create a MemReq here so we can do a translation.  This
 241     // will casue a TLB miss trap if necessary... not sure whether
 242     // that's the best thing to do or not.  We don't really need the
 243     // MemReq otherwise, since wh64 has no functional effect.
 244 /*
 245     MemReqPtr req = new MemReq(addr, thread->getXCProxy(), size, flags);
 246     req->asid = asid;
 247
 248     fault = cpu->translateDataWriteReq(req);
 249
 250     if (fault == NoFault && !(req->flags & UNCACHEABLE)) {
 251         // Record key MemReq parameters so we can generate another one
 252         // just like it for the timing access without calling translate()
 253         // again (which might mess up the TLB).
 254         effAddr = req->vaddr;
 255         physEffAddr = req->paddr;
 256         memReqFlags = req->flags;
 257     } else {
 258         // ignore faults & accesses to uncacheable space... treat as no-op
 259         effAddr = physEffAddr = MemReq::inval_addr;
 260     }
 261
 262     storeSize = size;
 263     storeData = 0;
 264 */
 265 }
 266
 267 /**
 268  * @todo Need to find a way to get the cache block size here.
 269  */
 270 template <class Impl>
 271 Fault
 272 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 273 {
 274 /*
 275     MemReqPtr req = new MemReq(src, thread->getXCProxy(), 64);
 276     req->asid = asid;
 277
 278     // translate to physical address
 279     Fault fault = cpu->translateDataReadReq(req);
 280
 281     if (fault == NoFault) {
 282         thread->copySrcAddr = src;
 283         thread->copySrcPhysAddr = req->paddr;
 284     } else {
 285         thread->copySrcAddr = 0;
 286         thread->copySrcPhysAddr = 0;
 287     }
 288     return fault;
 289 */
 290     return NoFault;
 291 }
 292
 293 /**
 294  * @todo Need to find a way to get the cache block size here.
 295  */
 296 template <class Impl>
 297 Fault
 298 BaseDynInst<Impl>::copy(Addr dest)
 299 {
 300 /*
 301     uint8_t data[64];
 302     FunctionalMemory *mem = thread->mem;
 303     assert(thread->copySrcPhysAddr);
 304     MemReqPtr req = new MemReq(dest, thread->getXCProxy(), 64);
 305     req->asid = asid;
 306
 307     // translate to physical address
 308     Fault fault = cpu->translateDataWriteReq(req);
 309
 310     if (fault == NoFault) {
 311         Addr dest_addr = req->paddr;
 312         // Need to read straight from memory since we have more than 8 bytes.
 313         req->paddr = thread->copySrcPhysAddr;
 314         mem->read(req, data);
 315         req->paddr = dest_addr;
 316         mem->write(req, data);
 317     }
 318     return fault;
 319 */
 320     return NoFault;
 321 }
 322
 323 template <class Impl>
 324 void
 325 BaseDynInst<Impl>::dump()
 326 {
 327     cprintf("T%d : %#08d `", threadNumber, PC);
 328     cout << staticInst->disassemble(PC);
 329     cprintf("'\n");
 330 }
 331
 332 template <class Impl>
 333 void
 334 BaseDynInst<Impl>::dump(std::string &outstring)
 335 {
 336     std::ostringstream s;
 337     s << "T" << threadNumber << " : 0x" << PC << " "
 338       << staticInst->disassemble(PC);
 339
 340     outstring = s.str();
 341 }
 342
 343 #if 0
 344 template <class Impl>
 345 Fault
 346 BaseDynInst<Impl>::mem_access(mem_cmd cmd, Addr addr, void *p, int nbytes)
 347 {
 348     Fault fault;
 349
 350     // check alignments, even speculative this test should always pass
 351     if ((nbytes & nbytes - 1) != 0 || (addr & nbytes - 1) != 0) {
 352         for (int i = 0; i < nbytes; i++)
 353             ((char *) p)[i] = 0;
 354
 355         // I added the following because according to the comment above,
 356         // we should never get here.  The comment lies
 357 #if 0
 358         panic("unaligned access. Cycle = %n", curTick);
 359 #endif
 360         return NoFault;
 361     }
 362
 363     MemReqPtr req = new MemReq(addr, thread, nbytes);
 364     switch(cmd) {
 365       case Read:
 366         fault = spec_mem->read(req, (uint8_t *)p);
 367         break;
 368
 369       case Write:
 370         fault = spec_mem->write(req, (uint8_t *)p);
 371         if (fault != NoFault)
 372             break;
 373
 374         specMemWrite = true;
 375         storeSize = nbytes;
 376         switch(nbytes) {
 377           case sizeof(uint8_t):
 378             *(uint8_t)&storeData = (uint8_t *)p;
 379             break;
 380           case sizeof(uint16_t):
 381             *(uint16_t)&storeData = (uint16_t *)p;
 382             break;
 383           case sizeof(uint32_t):
 384             *(uint32_t)&storeData = (uint32_t *)p;
 385             break;
 386           case sizeof(uint64_t):
 387             *(uint64_t)&storeData = (uint64_t *)p;
 388             break;
 389         }
 390         break;
 391
 392       default:
 393         fault = genMachineCheckFault();
 394         break;
 395     }
 396
 397     trace_mem(fault, cmd, addr, p, nbytes);
 398
 399     return fault;
 400 }
 401
 402 #endif
 403
 404 template <class Impl>
 405 void
 406 BaseDynInst<Impl>::markSrcRegReady()
 407 {
 408     if (++readyRegs == numSrcRegs()) {
 409         canIssue = true;
 410     }
 411 }
 412
 413 template <class Impl>
 414 void
 415 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 416 {
 417     ++readyRegs;
 418
 419     _readySrcRegIdx[src_idx] = true;
 420
 421     if (readyRegs == numSrcRegs()) {
 422         canIssue = true;
 423     }
 424 }
 425
 426 template <class Impl>
 427 bool
 428 BaseDynInst<Impl>::eaSrcsReady()
 429 {
 430     // For now I am assuming that src registers 1..n-1 are the ones that the
 431     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 432     // stored)
 433
 434     for (int i = 1; i < numSrcRegs(); ++i) {
 435         if (!_readySrcRegIdx[i])
 436             return false;
 437     }
 438
 439     return true;
 440 }
 441
 442 // Forward declaration
 443 template class BaseDynInst<AlphaSimpleImpl>;
 444
 445 template <>
 446 int
 447 BaseDynInst<AlphaSimpleImpl>::instcount = 0;
 448 /*
 449 // Forward declaration
 450 template class BaseDynInst<SimpleImpl>;
 451
 452 template <>
 453 int
 454 BaseDynInst<SimpleImpl>::instcount = 0;
 455
 456 // Forward declaration
 457 template class BaseDynInst<OzoneImpl>;
 458
 459 template <>
 460 int
 461 BaseDynInst<OzoneImpl>::instcount = 0;
 462 */