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46 #ifndef __CPU_BASE_DYN_INST_HH__
47 #define __CPU_BASE_DYN_INST_HH__
54 #include "arch/utility.hh"
55 #include "base/trace.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/checker/cpu.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/fault_fwd.hh"
67 #include "sim/system.hh"
72 * Defines a dynamic instruction context.
76 class BaseDynInst : public RefCounted
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
105 void set(uint64_t i) { integer = i; }
106 void set(double d) { dbl = d; }
107 void get(uint64_t& i) { i = integer; }
108 void get(double& d) { d = dbl; }
113 IqEntry, /// Instruction is in the IQ
114 RobEntry, /// Instruction is in the ROB
115 LsqEntry, /// Instruction is in the LSQ
116 Completed, /// Instruction has completed
117 ResultReady, /// Instruction has its result
118 CanIssue, /// Instruction can issue and execute
119 Issued, /// Instruction has issued
120 Executed, /// Instruction has executed
121 CanCommit, /// Instruction can commit
122 AtCommit, /// Instruction has reached commit
123 Committed, /// Instruction has committed
124 Squashed, /// Instruction is squashed
125 SquashedInIQ, /// Instruction is squashed in the IQ
126 SquashedInLSQ, /// Instruction is squashed in the LSQ
127 SquashedInROB, /// Instruction is squashed in the ROB
128 RecoverInst, /// Is a recover instruction
129 BlockingInst, /// Is a blocking instruction
130 ThreadsyncWait, /// Is a thread synchronization instruction
131 SerializeBefore, /// Needs to serialize on
132 /// instructions ahead of it
133 SerializeAfter, /// Needs to serialize instructions behind it
134 SerializeHandled, /// Serialization has been handled
140 TranslationCompleted,
141 PossibleLoadViolation,
147 /** Whether or not the effective address calculation is completed.
148 * @todo: Consider if this is necessary or not.
158 /** The sequence number of the instruction. */
161 /** The StaticInst used by this BaseDynInst. */
162 StaticInstPtr staticInst;
164 /** Pointer to the Impl's CPU object. */
167 BaseCPU *getCpuPtr() { return cpu; }
169 /** Pointer to the thread state. */
172 /** The kind of fault this instruction has generated. */
175 /** InstRecord that tracks this instructions. */
176 Trace::InstRecord *traceData;
179 /** The result of the instruction; assumes an instruction can have many
180 * destination registers.
182 std::queue<Result> instResult;
184 /** PC state for this instruction. */
187 /* An amalgamation of a lot of boolean values into one */
188 std::bitset<MaxFlags> instFlags;
190 /** The status of this BaseDynInst. Several bits can be set. */
191 std::bitset<NumStatus> status;
193 /** Whether or not the source register is ready.
194 * @todo: Not sure this should be here vs the derived class.
196 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
199 /** The thread this instruction is from. */
200 ThreadID threadNumber;
202 /** Iterator pointing to this BaseDynInst in the list of all insts. */
205 ////////////////////// Branch Data ///////////////
206 /** Predicted PC state after this instruction. */
207 TheISA::PCState predPC;
209 /** The Macroop if one exists */
210 StaticInstPtr macroop;
212 /** How many source registers are ready. */
216 /////////////////////// Load Store Data //////////////////////
217 /** The effective virtual address (lds & stores only). */
220 /** The effective physical address. */
223 /** The memory request flags (from translation). */
224 unsigned memReqFlags;
226 /** data address space ID, for loads & stores. */
229 /** The size of the request */
232 /** Pointer to the data for the memory access. */
235 /** Load queue index. */
238 /** Store queue index. */
242 /////////////////////// TLB Miss //////////////////////
244 * Saved memory requests (needed when the DTB address translation is
245 * delayed due to a hw page table walk).
248 RequestPtr savedSreqLow;
249 RequestPtr savedSreqHigh;
251 /////////////////////// Checker //////////////////////
252 // Need a copy of main request pointer to verify on writes.
253 RequestPtr reqToVerify;
256 /** Instruction effective address.
257 * @todo: Consider if this is necessary or not.
262 /** Flattened register index of the destination registers of this
265 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
267 /** Physical register index of the destination registers of this
270 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
272 /** Physical register index of the source registers of this
275 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
277 /** Physical register index of the previous producers of the
278 * architected destinations.
280 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
284 /** Records changes to result? */
285 void recordResult(bool f) { instFlags[RecordResult] = f; }
287 /** Is the effective virtual address valid. */
288 bool effAddrValid() const { return instFlags[EffAddrValid]; }
290 /** Whether or not the memory operation is done. */
291 bool memOpDone() const { return instFlags[MemOpDone]; }
292 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
295 ////////////////////////////////////////////
297 // INSTRUCTION EXECUTION
299 ////////////////////////////////////////////
301 void demapPage(Addr vaddr, uint64_t asn)
303 cpu->demapPage(vaddr, asn);
305 void demapInstPage(Addr vaddr, uint64_t asn)
307 cpu->demapPage(vaddr, asn);
309 void demapDataPage(Addr vaddr, uint64_t asn)
311 cpu->demapPage(vaddr, asn);
314 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
316 Fault writeMem(uint8_t *data, unsigned size,
317 Addr addr, unsigned flags, uint64_t *res);
319 /** Splits a request in two if it crosses a dcache block. */
320 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
321 RequestPtr &sreqHigh);
323 /** Initiate a DTB address translation. */
324 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
325 RequestPtr sreqHigh, uint64_t *res,
328 /** Finish a DTB address translation. */
329 void finishTranslation(WholeTranslationState *state);
331 /** True if the DTB address translation has started. */
332 bool translationStarted() const { return instFlags[TranslationStarted]; }
333 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
335 /** True if the DTB address translation has completed. */
336 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
337 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
339 /** True if this address was found to match a previous load and they issued
340 * out of order. If that happend, then it's only a problem if an incoming
341 * snoop invalidate modifies the line, in which case we need to squash.
342 * If nothing modified the line the order doesn't matter.
344 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
345 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
347 /** True if the address hit a external snoop while sitting in the LSQ.
348 * If this is true and a older instruction sees it, this instruction must
351 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
352 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
355 * Returns true if the DTB address translation is being delayed due to a hw
358 bool isTranslationDelayed() const
360 return (translationStarted() && !translationCompleted());
368 /** Returns the physical register index of the i'th destination
371 PhysRegIndex renamedDestRegIdx(int idx) const
373 return _destRegIdx[idx];
376 /** Returns the physical register index of the i'th source register. */
377 PhysRegIndex renamedSrcRegIdx(int idx) const
379 assert(TheISA::MaxInstSrcRegs > idx);
380 return _srcRegIdx[idx];
383 /** Returns the flattened register index of the i'th destination
386 TheISA::RegIndex flattenedDestRegIdx(int idx) const
388 return _flatDestRegIdx[idx];
391 /** Returns the physical register index of the previous physical register
392 * that remapped to the same logical register index.
394 PhysRegIndex prevDestRegIdx(int idx) const
396 return _prevDestRegIdx[idx];
399 /** Renames a destination register to a physical register. Also records
400 * the previous physical register that the logical register mapped to.
402 void renameDestReg(int idx,
403 PhysRegIndex renamed_dest,
404 PhysRegIndex previous_rename)
406 _destRegIdx[idx] = renamed_dest;
407 _prevDestRegIdx[idx] = previous_rename;
410 /** Renames a source logical register to the physical register which
411 * has/will produce that logical register's result.
412 * @todo: add in whether or not the source register is ready.
414 void renameSrcReg(int idx, PhysRegIndex renamed_src)
416 _srcRegIdx[idx] = renamed_src;
419 /** Flattens a destination architectural register index into a logical
422 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
424 _flatDestRegIdx[idx] = flattened_dest;
426 /** BaseDynInst constructor given a binary instruction.
427 * @param staticInst A StaticInstPtr to the underlying instruction.
428 * @param pc The PC state for the instruction.
429 * @param predPC The predicted next PC state for the instruction.
430 * @param seq_num The sequence number of the instruction.
431 * @param cpu Pointer to the instruction's CPU.
433 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
434 TheISA::PCState pc, TheISA::PCState predPC,
435 InstSeqNum seq_num, ImplCPU *cpu);
437 /** BaseDynInst constructor given a StaticInst pointer.
438 * @param _staticInst The StaticInst for this BaseDynInst.
440 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
442 /** BaseDynInst destructor. */
446 /** Function to initialize variables in the constructors. */
450 /** Dumps out contents of this BaseDynInst. */
453 /** Dumps out contents of this BaseDynInst into given string. */
454 void dump(std::string &outstring);
456 /** Read this CPU's ID. */
457 int cpuId() { return cpu->cpuId(); }
459 /** Read this CPU's data requestor ID */
460 MasterID masterId() { return cpu->dataMasterId(); }
462 /** Read this context's system-wide ID **/
463 int contextId() { return thread->contextId(); }
465 /** Returns the fault type. */
466 Fault getFault() { return fault; }
468 /** Checks whether or not this instruction has had its branch target
469 * calculated yet. For now it is not utilized and is hacked to be
471 * @todo: Actually use this instruction.
473 bool doneTargCalc() { return false; }
475 /** Set the predicted target of this current instruction. */
476 void setPredTarg(const TheISA::PCState &_predPC)
481 const TheISA::PCState &readPredTarg() { return predPC; }
483 /** Returns the predicted PC immediately after the branch. */
484 Addr predInstAddr() { return predPC.instAddr(); }
486 /** Returns the predicted PC two instructions after the branch */
487 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
489 /** Returns the predicted micro PC after the branch */
490 Addr predMicroPC() { return predPC.microPC(); }
492 /** Returns whether the instruction was predicted taken or not. */
495 return instFlags[PredTaken];
498 void setPredTaken(bool predicted_taken)
500 instFlags[PredTaken] = predicted_taken;
503 /** Returns whether the instruction mispredicted. */
506 TheISA::PCState tempPC = pc;
507 TheISA::advancePC(tempPC, staticInst);
508 return !(tempPC == predPC);
512 // Instruction types. Forward checks to StaticInst object.
514 bool isNop() const { return staticInst->isNop(); }
515 bool isMemRef() const { return staticInst->isMemRef(); }
516 bool isLoad() const { return staticInst->isLoad(); }
517 bool isStore() const { return staticInst->isStore(); }
518 bool isStoreConditional() const
519 { return staticInst->isStoreConditional(); }
520 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
521 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
522 bool isInteger() const { return staticInst->isInteger(); }
523 bool isFloating() const { return staticInst->isFloating(); }
524 bool isControl() const { return staticInst->isControl(); }
525 bool isCall() const { return staticInst->isCall(); }
526 bool isReturn() const { return staticInst->isReturn(); }
527 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
528 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
529 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
530 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
531 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
532 bool isThreadSync() const { return staticInst->isThreadSync(); }
533 bool isSerializing() const { return staticInst->isSerializing(); }
534 bool isSerializeBefore() const
535 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
536 bool isSerializeAfter() const
537 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
538 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
539 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
540 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
541 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
542 bool isQuiesce() const { return staticInst->isQuiesce(); }
543 bool isIprAccess() const { return staticInst->isIprAccess(); }
544 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
545 bool isSyscall() const { return staticInst->isSyscall(); }
546 bool isMacroop() const { return staticInst->isMacroop(); }
547 bool isMicroop() const { return staticInst->isMicroop(); }
548 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
549 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
550 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
551 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
553 /** Temporarily sets this instruction as a serialize before instruction. */
554 void setSerializeBefore() { status.set(SerializeBefore); }
556 /** Clears the serializeBefore part of this instruction. */
557 void clearSerializeBefore() { status.reset(SerializeBefore); }
559 /** Checks if this serializeBefore is only temporarily set. */
560 bool isTempSerializeBefore() { return status[SerializeBefore]; }
562 /** Temporarily sets this instruction as a serialize after instruction. */
563 void setSerializeAfter() { status.set(SerializeAfter); }
565 /** Clears the serializeAfter part of this instruction.*/
566 void clearSerializeAfter() { status.reset(SerializeAfter); }
568 /** Checks if this serializeAfter is only temporarily set. */
569 bool isTempSerializeAfter() { return status[SerializeAfter]; }
571 /** Sets the serialization part of this instruction as handled. */
572 void setSerializeHandled() { status.set(SerializeHandled); }
574 /** Checks if the serialization part of this instruction has been
575 * handled. This does not apply to the temporary serializing
576 * state; it only applies to this instruction's own permanent
579 bool isSerializeHandled() { return status[SerializeHandled]; }
581 /** Returns the opclass of this instruction. */
582 OpClass opClass() const { return staticInst->opClass(); }
584 /** Returns the branch target address. */
585 TheISA::PCState branchTarget() const
586 { return staticInst->branchTarget(pc); }
588 /** Returns the number of source registers. */
589 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
591 /** Returns the number of destination registers. */
592 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
594 // the following are used to track physical register usage
595 // for machines with separate int & FP reg files
596 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
597 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
599 /** Returns the logical register index of the i'th destination register. */
600 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
602 /** Returns the logical register index of the i'th source register. */
603 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
605 /** Pops a result off the instResult queue */
609 if (!instResult.empty()) {
610 instResult.front().get(t);
615 /** Read the most recent result stored by this instruction */
617 void readResult(T& t)
619 instResult.back().get(t);
622 /** Pushes a result onto the instResult queue */
626 if (instFlags[RecordResult]) {
629 instResult.push(instRes);
633 /** Records an integer register being set to a value. */
634 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
636 setResult<uint64_t>(val);
639 /** Records a CC register being set to a value. */
640 void setCCRegOperand(const StaticInst *si, int idx, uint64_t val)
642 setResult<uint64_t>(val);
645 /** Records an fp register being set to a value. */
646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
649 if (width == 32 || width == 64) {
650 setResult<double>(val);
652 panic("Unsupported width!");
656 /** Records an fp register being set to a value. */
657 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
659 setResult<double>(val);
662 /** Records an fp register being set to an integer value. */
663 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
666 setResult<uint64_t>(val);
669 /** Records an fp register being set to an integer value. */
670 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
672 setResult<uint64_t>(val);
675 /** Records that one of the source registers is ready. */
676 void markSrcRegReady();
678 /** Marks a specific register as ready. */
679 void markSrcRegReady(RegIndex src_idx);
681 /** Returns if a source register is ready. */
682 bool isReadySrcRegIdx(int idx) const
684 return this->_readySrcRegIdx[idx];
687 /** Sets this instruction as completed. */
688 void setCompleted() { status.set(Completed); }
690 /** Returns whether or not this instruction is completed. */
691 bool isCompleted() const { return status[Completed]; }
693 /** Marks the result as ready. */
694 void setResultReady() { status.set(ResultReady); }
696 /** Returns whether or not the result is ready. */
697 bool isResultReady() const { return status[ResultReady]; }
699 /** Sets this instruction as ready to issue. */
700 void setCanIssue() { status.set(CanIssue); }
702 /** Returns whether or not this instruction is ready to issue. */
703 bool readyToIssue() const { return status[CanIssue]; }
705 /** Clears this instruction being able to issue. */
706 void clearCanIssue() { status.reset(CanIssue); }
708 /** Sets this instruction as issued from the IQ. */
709 void setIssued() { status.set(Issued); }
711 /** Returns whether or not this instruction has issued. */
712 bool isIssued() const { return status[Issued]; }
714 /** Clears this instruction as being issued. */
715 void clearIssued() { status.reset(Issued); }
717 /** Sets this instruction as executed. */
718 void setExecuted() { status.set(Executed); }
720 /** Returns whether or not this instruction has executed. */
721 bool isExecuted() const { return status[Executed]; }
723 /** Sets this instruction as ready to commit. */
724 void setCanCommit() { status.set(CanCommit); }
726 /** Clears this instruction as being ready to commit. */
727 void clearCanCommit() { status.reset(CanCommit); }
729 /** Returns whether or not this instruction is ready to commit. */
730 bool readyToCommit() const { return status[CanCommit]; }
732 void setAtCommit() { status.set(AtCommit); }
734 bool isAtCommit() { return status[AtCommit]; }
736 /** Sets this instruction as committed. */
737 void setCommitted() { status.set(Committed); }
739 /** Returns whether or not this instruction is committed. */
740 bool isCommitted() const { return status[Committed]; }
742 /** Sets this instruction as squashed. */
743 void setSquashed() { status.set(Squashed); }
745 /** Returns whether or not this instruction is squashed. */
746 bool isSquashed() const { return status[Squashed]; }
748 //Instruction Queue Entry
749 //-----------------------
750 /** Sets this instruction as a entry the IQ. */
751 void setInIQ() { status.set(IqEntry); }
753 /** Sets this instruction as a entry the IQ. */
754 void clearInIQ() { status.reset(IqEntry); }
756 /** Returns whether or not this instruction has issued. */
757 bool isInIQ() const { return status[IqEntry]; }
759 /** Sets this instruction as squashed in the IQ. */
760 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
762 /** Returns whether or not this instruction is squashed in the IQ. */
763 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
766 //Load / Store Queue Functions
767 //-----------------------
768 /** Sets this instruction as a entry the LSQ. */
769 void setInLSQ() { status.set(LsqEntry); }
771 /** Sets this instruction as a entry the LSQ. */
772 void removeInLSQ() { status.reset(LsqEntry); }
774 /** Returns whether or not this instruction is in the LSQ. */
775 bool isInLSQ() const { return status[LsqEntry]; }
777 /** Sets this instruction as squashed in the LSQ. */
778 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
780 /** Returns whether or not this instruction is squashed in the LSQ. */
781 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
784 //Reorder Buffer Functions
785 //-----------------------
786 /** Sets this instruction as a entry the ROB. */
787 void setInROB() { status.set(RobEntry); }
789 /** Sets this instruction as a entry the ROB. */
790 void clearInROB() { status.reset(RobEntry); }
792 /** Returns whether or not this instruction is in the ROB. */
793 bool isInROB() const { return status[RobEntry]; }
795 /** Sets this instruction as squashed in the ROB. */
796 void setSquashedInROB() { status.set(SquashedInROB); }
798 /** Returns whether or not this instruction is squashed in the ROB. */
799 bool isSquashedInROB() const { return status[SquashedInROB]; }
801 /** Read the PC state of this instruction. */
802 const TheISA::PCState pcState() const { return pc; }
804 /** Set the PC state of this instruction. */
805 const void pcState(const TheISA::PCState &val) { pc = val; }
807 /** Read the PC of this instruction. */
808 const Addr instAddr() const { return pc.instAddr(); }
810 /** Read the PC of the next instruction. */
811 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
813 /**Read the micro PC of this instruction. */
814 const Addr microPC() const { return pc.microPC(); }
818 return instFlags[Predicate];
821 void setPredicate(bool val)
823 instFlags[Predicate] = val;
826 traceData->setPredicate(val);
830 /** Sets the ASID. */
831 void setASID(short addr_space_id) { asid = addr_space_id; }
833 /** Sets the thread id. */
834 void setTid(ThreadID tid) { threadNumber = tid; }
836 /** Sets the pointer to the thread state. */
837 void setThreadState(ImplState *state) { thread = state; }
839 /** Returns the thread context. */
840 ThreadContext *tcBase() { return thread->getTC(); }
843 /** Sets the effective address. */
844 void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
846 /** Returns the effective address. */
847 const Addr &getEA() const { return instEffAddr; }
849 /** Returns whether or not the eff. addr. calculation has been completed. */
850 bool doneEACalc() { return instFlags[EACalcDone]; }
852 /** Returns whether or not the eff. addr. source registers are ready. */
855 /** Is this instruction's memory access uncacheable. */
856 bool uncacheable() { return instFlags[IsUncacheable]; }
858 /** Has this instruction generated a memory request. */
859 bool hasRequest() { return instFlags[ReqMade]; }
861 /** Returns iterator to this instruction in the list of all insts. */
862 ListIt &getInstListIt() { return instListIt; }
864 /** Sets iterator for this instruction in the list of all insts. */
865 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
868 /** Returns the number of consecutive store conditional failures. */
869 unsigned readStCondFailures()
870 { return thread->storeCondFailures; }
872 /** Sets the number of consecutive store conditional failures. */
873 void setStCondFailures(unsigned sc_failures)
874 { thread->storeCondFailures = sc_failures; }
879 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
880 unsigned size, unsigned flags)
882 instFlags[ReqMade] = true;
884 Request *sreqLow = NULL;
885 Request *sreqHigh = NULL;
887 if (instFlags[ReqMade] && translationStarted()) {
889 sreqLow = savedSreqLow;
890 sreqHigh = savedSreqHigh;
892 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
893 thread->contextId(), threadNumber);
895 req->taskId(cpu->taskId());
897 // Only split the request if the ISA supports unaligned accesses.
898 if (TheISA::HasUnalignedMemAcc) {
899 splitRequest(req, sreqLow, sreqHigh);
901 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
904 if (translationCompleted()) {
905 if (fault == NoFault) {
906 effAddr = req->getVaddr();
908 instFlags[EffAddrValid] = true;
911 if (reqToVerify != NULL) {
914 reqToVerify = new Request(*req);
916 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
918 // Commit will have to clean up whatever happened. Set this
919 // instruction as executed.
923 if (fault != NoFault) {
924 // Return a fixed value to keep simulation deterministic even
925 // along misspeculated paths.
932 traceData->setAddr(addr);
940 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
941 Addr addr, unsigned flags, uint64_t *res)
944 traceData->setAddr(addr);
947 instFlags[ReqMade] = true;
949 Request *sreqLow = NULL;
950 Request *sreqHigh = NULL;
952 if (instFlags[ReqMade] && translationStarted()) {
954 sreqLow = savedSreqLow;
955 sreqHigh = savedSreqHigh;
957 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
958 thread->contextId(), threadNumber);
960 req->taskId(cpu->taskId());
962 // Only split the request if the ISA supports unaligned accesses.
963 if (TheISA::HasUnalignedMemAcc) {
964 splitRequest(req, sreqLow, sreqHigh);
966 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
969 if (fault == NoFault && translationCompleted()) {
970 effAddr = req->getVaddr();
972 instFlags[EffAddrValid] = true;
975 if (reqToVerify != NULL) {
978 reqToVerify = new Request(*req);
980 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
988 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
989 RequestPtr &sreqHigh)
991 // Check to see if the request crosses the next level block boundary.
992 unsigned block_size = cpu->cacheLineSize();
993 Addr addr = req->getVaddr();
994 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
995 assert(split_addr <= addr || split_addr - addr < block_size);
998 if (split_addr > addr) {
999 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1003 template<class Impl>
1005 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1006 RequestPtr sreqHigh, uint64_t *res,
1009 translationStarted(true);
1011 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1012 WholeTranslationState *state =
1013 new WholeTranslationState(req, NULL, res, mode);
1015 // One translation if the request isn't split.
1016 DataTranslation<BaseDynInstPtr> *trans =
1017 new DataTranslation<BaseDynInstPtr>(this, state);
1019 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1021 if (!translationCompleted()) {
1022 // The translation isn't yet complete, so we can't possibly have a
1023 // fault. Overwrite any existing fault we might have from a previous
1024 // execution of this instruction (e.g. an uncachable load that
1025 // couldn't execute because it wasn't at the head of the ROB).
1028 // Save memory requests.
1029 savedReq = state->mainReq;
1030 savedSreqLow = state->sreqLow;
1031 savedSreqHigh = state->sreqHigh;
1034 WholeTranslationState *state =
1035 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1037 // Two translations when the request is split.
1038 DataTranslation<BaseDynInstPtr> *stransLow =
1039 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1040 DataTranslation<BaseDynInstPtr> *stransHigh =
1041 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1043 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1044 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1046 if (!translationCompleted()) {
1047 // The translation isn't yet complete, so we can't possibly have a
1048 // fault. Overwrite any existing fault we might have from a previous
1049 // execution of this instruction (e.g. an uncachable load that
1050 // couldn't execute because it wasn't at the head of the ROB).
1053 // Save memory requests.
1054 savedReq = state->mainReq;
1055 savedSreqLow = state->sreqLow;
1056 savedSreqHigh = state->sreqHigh;
1061 template<class Impl>
1063 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1065 fault = state->getFault();
1067 instFlags[IsUncacheable] = state->isUncacheable();
1069 if (fault == NoFault) {
1070 physEffAddr = state->getPaddr();
1071 memReqFlags = state->getFlags();
1073 if (state->mainReq->isCondSwap()) {
1075 state->mainReq->setExtraData(*state->res);
1079 state->deleteReqs();
1083 translationCompleted(true);
1086 #endif // __CPU_BASE_DYN_INST_HH__