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45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
52 #include "arch/faults.hh"
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/full_system.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/system.hh"
71 * Defines a dynamic instruction context.
74 // Forward declaration.
78 class BaseDynInst : public FastAlloc, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
92 // The DynInstPtr type.
93 typedef typename Impl::DynInstPtr DynInstPtr;
95 // The list of instructions iterator type.
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
99 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
100 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
103 /** The StaticInst used by this BaseDynInst. */
104 StaticInstPtr staticInst;
106 ////////////////////////////////////////////
108 // INSTRUCTION EXECUTION
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
114 void demapPage(Addr vaddr, uint64_t asn)
116 cpu->demapPage(vaddr, asn);
118 void demapInstPage(Addr vaddr, uint64_t asn)
120 cpu->demapPage(vaddr, asn);
122 void demapDataPage(Addr vaddr, uint64_t asn)
124 cpu->demapPage(vaddr, asn);
128 * Does a read to a given address.
129 * @param addr The address to read.
130 * @param data The read's data is written into this parameter.
131 * @param flags The request's flags.
132 * @return Returns any fault due to the read.
135 Fault read(Addr addr, T &data, unsigned flags);
137 Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
140 * Does a write to a given address.
141 * @param data The data to be written.
142 * @param addr The address to write to.
143 * @param flags The request's flags.
144 * @param res The result of the write (for load locked/store conditionals).
145 * @return Returns any fault due to the write.
148 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
150 Fault writeBytes(uint8_t *data, unsigned size,
151 Addr addr, unsigned flags, uint64_t *res);
153 /** Splits a request in two if it crosses a dcache block. */
154 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
155 RequestPtr &sreqHigh);
157 /** Initiate a DTB address translation. */
158 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
159 RequestPtr sreqHigh, uint64_t *res,
162 /** Finish a DTB address translation. */
163 void finishTranslation(WholeTranslationState *state);
165 /** True if the DTB address translation has started. */
166 bool translationStarted;
168 /** True if the DTB address translation has completed. */
169 bool translationCompleted;
172 * Returns true if the DTB address translation is being delayed due to a hw
175 bool isTranslationDelayed() const
177 return (translationStarted && !translationCompleted);
181 * Saved memory requests (needed when the DTB address translation is
182 * delayed due to a hw page table walk).
185 RequestPtr savedSreqLow;
186 RequestPtr savedSreqHigh;
188 /** @todo: Consider making this private. */
190 /** The sequence number of the instruction. */
194 IqEntry, /// Instruction is in the IQ
195 RobEntry, /// Instruction is in the ROB
196 LsqEntry, /// Instruction is in the LSQ
197 Completed, /// Instruction has completed
198 ResultReady, /// Instruction has its result
199 CanIssue, /// Instruction can issue and execute
200 Issued, /// Instruction has issued
201 Executed, /// Instruction has executed
202 CanCommit, /// Instruction can commit
203 AtCommit, /// Instruction has reached commit
204 Committed, /// Instruction has committed
205 Squashed, /// Instruction is squashed
206 SquashedInIQ, /// Instruction is squashed in the IQ
207 SquashedInLSQ, /// Instruction is squashed in the LSQ
208 SquashedInROB, /// Instruction is squashed in the ROB
209 RecoverInst, /// Is a recover instruction
210 BlockingInst, /// Is a blocking instruction
211 ThreadsyncWait, /// Is a thread synchronization instruction
212 SerializeBefore, /// Needs to serialize on
213 /// instructions ahead of it
214 SerializeAfter, /// Needs to serialize instructions behind it
215 SerializeHandled, /// Serialization has been handled
219 /** The status of this BaseDynInst. Several bits can be set. */
220 std::bitset<NumStatus> status;
222 /** The thread this instruction is from. */
223 ThreadID threadNumber;
225 /** data address space ID, for loads & stores. */
228 /** How many source registers are ready. */
231 /** Pointer to the Impl's CPU object. */
234 /** Pointer to the thread state. */
237 /** The kind of fault this instruction has generated. */
240 /** Pointer to the data for the memory access. */
243 /** The effective virtual address (lds & stores only). */
246 /** The size of the request */
249 /** Is the effective virtual address valid. */
252 /** The effective physical address. */
255 /** The memory request flags (from translation). */
256 unsigned memReqFlags;
264 /** The result of the instruction; assumes for now that there's only one
265 * destination register.
269 /** Records changes to result? */
272 /** Did this instruction execute, or is it predicated false */
276 /** PC state for this instruction. */
279 /** Predicted PC state after this instruction. */
280 TheISA::PCState predPC;
282 /** If this is a branch that was predicted taken */
291 /** Whether or not the source register is ready.
292 * @todo: Not sure this should be here vs the derived class.
294 bool _readySrcRegIdx[MaxInstSrcRegs];
297 /** Flattened register index of the destination registers of this
300 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
302 /** Flattened register index of the source registers of this
305 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
307 /** Physical register index of the destination registers of this
310 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
312 /** Physical register index of the source registers of this
315 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
317 /** Physical register index of the previous producers of the
318 * architected destinations.
320 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
324 /** Returns the physical register index of the i'th destination
327 PhysRegIndex renamedDestRegIdx(int idx) const
329 return _destRegIdx[idx];
332 /** Returns the physical register index of the i'th source register. */
333 PhysRegIndex renamedSrcRegIdx(int idx) const
335 return _srcRegIdx[idx];
338 /** Returns the flattened register index of the i'th destination
341 TheISA::RegIndex flattenedDestRegIdx(int idx) const
343 return _flatDestRegIdx[idx];
346 /** Returns the flattened register index of the i'th source register */
347 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
349 return _flatSrcRegIdx[idx];
352 /** Returns the physical register index of the previous physical register
353 * that remapped to the same logical register index.
355 PhysRegIndex prevDestRegIdx(int idx) const
357 return _prevDestRegIdx[idx];
360 /** Renames a destination register to a physical register. Also records
361 * the previous physical register that the logical register mapped to.
363 void renameDestReg(int idx,
364 PhysRegIndex renamed_dest,
365 PhysRegIndex previous_rename)
367 _destRegIdx[idx] = renamed_dest;
368 _prevDestRegIdx[idx] = previous_rename;
371 /** Renames a source logical register to the physical register which
372 * has/will produce that logical register's result.
373 * @todo: add in whether or not the source register is ready.
375 void renameSrcReg(int idx, PhysRegIndex renamed_src)
377 _srcRegIdx[idx] = renamed_src;
380 /** Flattens a source architectural register index into a logical index.
382 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
384 _flatSrcRegIdx[idx] = flattened_src;
387 /** Flattens a destination architectural register index into a logical
390 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
392 _flatDestRegIdx[idx] = flattened_dest;
394 /** BaseDynInst constructor given a binary instruction.
395 * @param staticInst A StaticInstPtr to the underlying instruction.
396 * @param pc The PC state for the instruction.
397 * @param predPC The predicted next PC state for the instruction.
398 * @param seq_num The sequence number of the instruction.
399 * @param cpu Pointer to the instruction's CPU.
401 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
402 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
404 /** BaseDynInst constructor given a binary instruction.
405 * @param inst The binary instruction.
406 * @param _pc The PC state for the instruction.
407 * @param _predPC The predicted next PC state for the instruction.
408 * @param seq_num The sequence number of the instruction.
409 * @param cpu Pointer to the instruction's CPU.
411 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
412 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
414 /** BaseDynInst constructor given a StaticInst pointer.
415 * @param _staticInst The StaticInst for this BaseDynInst.
417 BaseDynInst(StaticInstPtr &_staticInst);
419 /** BaseDynInst destructor. */
423 /** Function to initialize variables in the constructors. */
427 /** Dumps out contents of this BaseDynInst. */
430 /** Dumps out contents of this BaseDynInst into given string. */
431 void dump(std::string &outstring);
433 /** Read this CPU's ID. */
434 int cpuId() { return cpu->cpuId(); }
436 /** Read this context's system-wide ID **/
437 int contextId() { return thread->contextId(); }
439 /** Returns the fault type. */
440 Fault getFault() { return fault; }
442 /** Checks whether or not this instruction has had its branch target
443 * calculated yet. For now it is not utilized and is hacked to be
445 * @todo: Actually use this instruction.
447 bool doneTargCalc() { return false; }
449 /** Set the predicted target of this current instruction. */
450 void setPredTarg(const TheISA::PCState &_predPC)
455 const TheISA::PCState &readPredTarg() { return predPC; }
457 /** Returns the predicted PC immediately after the branch. */
458 Addr predInstAddr() { return predPC.instAddr(); }
460 /** Returns the predicted PC two instructions after the branch */
461 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
463 /** Returns the predicted micro PC after the branch */
464 Addr predMicroPC() { return predPC.microPC(); }
466 /** Returns whether the instruction was predicted taken or not. */
472 void setPredTaken(bool predicted_taken)
474 predTaken = predicted_taken;
477 /** Returns whether the instruction mispredicted. */
480 TheISA::PCState tempPC = pc;
481 TheISA::advancePC(tempPC, staticInst);
482 return !(tempPC == predPC);
486 // Instruction types. Forward checks to StaticInst object.
488 bool isNop() const { return staticInst->isNop(); }
489 bool isMemRef() const { return staticInst->isMemRef(); }
490 bool isLoad() const { return staticInst->isLoad(); }
491 bool isStore() const { return staticInst->isStore(); }
492 bool isStoreConditional() const
493 { return staticInst->isStoreConditional(); }
494 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
495 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
496 bool isInteger() const { return staticInst->isInteger(); }
497 bool isFloating() const { return staticInst->isFloating(); }
498 bool isControl() const { return staticInst->isControl(); }
499 bool isCall() const { return staticInst->isCall(); }
500 bool isReturn() const { return staticInst->isReturn(); }
501 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
502 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
503 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
504 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
505 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
506 bool isThreadSync() const { return staticInst->isThreadSync(); }
507 bool isSerializing() const { return staticInst->isSerializing(); }
508 bool isSerializeBefore() const
509 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
510 bool isSerializeAfter() const
511 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
512 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
513 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
514 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
515 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
516 bool isQuiesce() const { return staticInst->isQuiesce(); }
517 bool isIprAccess() const { return staticInst->isIprAccess(); }
518 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
519 bool isSyscall() const { return staticInst->isSyscall(); }
520 bool isMacroop() const { return staticInst->isMacroop(); }
521 bool isMicroop() const { return staticInst->isMicroop(); }
522 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
523 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
524 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
525 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
527 /** Temporarily sets this instruction as a serialize before instruction. */
528 void setSerializeBefore() { status.set(SerializeBefore); }
530 /** Clears the serializeBefore part of this instruction. */
531 void clearSerializeBefore() { status.reset(SerializeBefore); }
533 /** Checks if this serializeBefore is only temporarily set. */
534 bool isTempSerializeBefore() { return status[SerializeBefore]; }
536 /** Temporarily sets this instruction as a serialize after instruction. */
537 void setSerializeAfter() { status.set(SerializeAfter); }
539 /** Clears the serializeAfter part of this instruction.*/
540 void clearSerializeAfter() { status.reset(SerializeAfter); }
542 /** Checks if this serializeAfter is only temporarily set. */
543 bool isTempSerializeAfter() { return status[SerializeAfter]; }
545 /** Sets the serialization part of this instruction as handled. */
546 void setSerializeHandled() { status.set(SerializeHandled); }
548 /** Checks if the serialization part of this instruction has been
549 * handled. This does not apply to the temporary serializing
550 * state; it only applies to this instruction's own permanent
553 bool isSerializeHandled() { return status[SerializeHandled]; }
555 /** Returns the opclass of this instruction. */
556 OpClass opClass() const { return staticInst->opClass(); }
558 /** Returns the branch target address. */
559 TheISA::PCState branchTarget() const
560 { return staticInst->branchTarget(pc); }
562 /** Returns the number of source registers. */
563 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
565 /** Returns the number of destination registers. */
566 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
568 // the following are used to track physical register usage
569 // for machines with separate int & FP reg files
570 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
571 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
573 /** Returns the logical register index of the i'th destination register. */
574 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
576 /** Returns the logical register index of the i'th source register. */
577 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
579 /** Returns the result of an integer instruction. */
580 uint64_t readIntResult() { return instResult.integer; }
582 /** Returns the result of a floating point instruction. */
583 float readFloatResult() { return (float)instResult.dbl; }
585 /** Returns the result of a floating point (double) instruction. */
586 double readDoubleResult() { return instResult.dbl; }
588 /** Records an integer register being set to a value. */
589 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
592 instResult.integer = val;
595 /** Records an fp register being set to a value. */
596 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
601 instResult.dbl = (double)val;
602 else if (width == 64)
603 instResult.dbl = val;
605 panic("Unsupported width!");
609 /** Records an fp register being set to a value. */
610 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
613 instResult.dbl = (double)val;
616 /** Records an fp register being set to an integer value. */
617 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
621 instResult.integer = val;
624 /** Records an fp register being set to an integer value. */
625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
628 instResult.integer = val;
631 /** Records that one of the source registers is ready. */
632 void markSrcRegReady();
634 /** Marks a specific register as ready. */
635 void markSrcRegReady(RegIndex src_idx);
637 /** Returns if a source register is ready. */
638 bool isReadySrcRegIdx(int idx) const
640 return this->_readySrcRegIdx[idx];
643 /** Sets this instruction as completed. */
644 void setCompleted() { status.set(Completed); }
646 /** Returns whether or not this instruction is completed. */
647 bool isCompleted() const { return status[Completed]; }
649 /** Marks the result as ready. */
650 void setResultReady() { status.set(ResultReady); }
652 /** Returns whether or not the result is ready. */
653 bool isResultReady() const { return status[ResultReady]; }
655 /** Sets this instruction as ready to issue. */
656 void setCanIssue() { status.set(CanIssue); }
658 /** Returns whether or not this instruction is ready to issue. */
659 bool readyToIssue() const { return status[CanIssue]; }
661 /** Clears this instruction being able to issue. */
662 void clearCanIssue() { status.reset(CanIssue); }
664 /** Sets this instruction as issued from the IQ. */
665 void setIssued() { status.set(Issued); }
667 /** Returns whether or not this instruction has issued. */
668 bool isIssued() const { return status[Issued]; }
670 /** Clears this instruction as being issued. */
671 void clearIssued() { status.reset(Issued); }
673 /** Sets this instruction as executed. */
674 void setExecuted() { status.set(Executed); }
676 /** Returns whether or not this instruction has executed. */
677 bool isExecuted() const { return status[Executed]; }
679 /** Sets this instruction as ready to commit. */
680 void setCanCommit() { status.set(CanCommit); }
682 /** Clears this instruction as being ready to commit. */
683 void clearCanCommit() { status.reset(CanCommit); }
685 /** Returns whether or not this instruction is ready to commit. */
686 bool readyToCommit() const { return status[CanCommit]; }
688 void setAtCommit() { status.set(AtCommit); }
690 bool isAtCommit() { return status[AtCommit]; }
692 /** Sets this instruction as committed. */
693 void setCommitted() { status.set(Committed); }
695 /** Returns whether or not this instruction is committed. */
696 bool isCommitted() const { return status[Committed]; }
698 /** Sets this instruction as squashed. */
699 void setSquashed() { status.set(Squashed); }
701 /** Returns whether or not this instruction is squashed. */
702 bool isSquashed() const { return status[Squashed]; }
704 //Instruction Queue Entry
705 //-----------------------
706 /** Sets this instruction as a entry the IQ. */
707 void setInIQ() { status.set(IqEntry); }
709 /** Sets this instruction as a entry the IQ. */
710 void clearInIQ() { status.reset(IqEntry); }
712 /** Returns whether or not this instruction has issued. */
713 bool isInIQ() const { return status[IqEntry]; }
715 /** Sets this instruction as squashed in the IQ. */
716 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
718 /** Returns whether or not this instruction is squashed in the IQ. */
719 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
722 //Load / Store Queue Functions
723 //-----------------------
724 /** Sets this instruction as a entry the LSQ. */
725 void setInLSQ() { status.set(LsqEntry); }
727 /** Sets this instruction as a entry the LSQ. */
728 void removeInLSQ() { status.reset(LsqEntry); }
730 /** Returns whether or not this instruction is in the LSQ. */
731 bool isInLSQ() const { return status[LsqEntry]; }
733 /** Sets this instruction as squashed in the LSQ. */
734 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
736 /** Returns whether or not this instruction is squashed in the LSQ. */
737 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
740 //Reorder Buffer Functions
741 //-----------------------
742 /** Sets this instruction as a entry the ROB. */
743 void setInROB() { status.set(RobEntry); }
745 /** Sets this instruction as a entry the ROB. */
746 void clearInROB() { status.reset(RobEntry); }
748 /** Returns whether or not this instruction is in the ROB. */
749 bool isInROB() const { return status[RobEntry]; }
751 /** Sets this instruction as squashed in the ROB. */
752 void setSquashedInROB() { status.set(SquashedInROB); }
754 /** Returns whether or not this instruction is squashed in the ROB. */
755 bool isSquashedInROB() const { return status[SquashedInROB]; }
757 /** Read the PC state of this instruction. */
758 const TheISA::PCState pcState() const { return pc; }
760 /** Set the PC state of this instruction. */
761 const void pcState(const TheISA::PCState &val) { pc = val; }
763 /** Read the PC of this instruction. */
764 const Addr instAddr() const { return pc.instAddr(); }
766 /** Read the PC of the next instruction. */
767 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
769 /**Read the micro PC of this instruction. */
770 const Addr microPC() const { return pc.microPC(); }
777 void setPredicate(bool val)
782 traceData->setPredicate(val);
786 /** Sets the ASID. */
787 void setASID(short addr_space_id) { asid = addr_space_id; }
789 /** Sets the thread id. */
790 void setTid(ThreadID tid) { threadNumber = tid; }
792 /** Sets the pointer to the thread state. */
793 void setThreadState(ImplState *state) { thread = state; }
795 /** Returns the thread context. */
796 ThreadContext *tcBase() { return thread->getTC(); }
799 /** Instruction effective address.
800 * @todo: Consider if this is necessary or not.
804 /** Whether or not the effective address calculation is completed.
805 * @todo: Consider if this is necessary or not.
809 /** Is this instruction's memory access uncacheable. */
812 /** Has this instruction generated a memory request. */
816 /** Sets the effective address. */
817 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
819 /** Returns the effective address. */
820 const Addr &getEA() const { return instEffAddr; }
822 /** Returns whether or not the eff. addr. calculation has been completed. */
823 bool doneEACalc() { return eaCalcDone; }
825 /** Returns whether or not the eff. addr. source registers are ready. */
828 /** Whether or not the memory operation is done. */
831 /** Is this instruction's memory access uncacheable. */
832 bool uncacheable() { return isUncacheable; }
834 /** Has this instruction generated a memory request. */
835 bool hasRequest() { return reqMade; }
838 /** Load queue index. */
841 /** Store queue index. */
844 /** Iterator pointing to this BaseDynInst in the list of all insts. */
847 /** Returns iterator to this instruction in the list of all insts. */
848 ListIt &getInstListIt() { return instListIt; }
850 /** Sets iterator for this instruction in the list of all insts. */
851 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
854 /** Returns the number of consecutive store conditional failures. */
855 unsigned readStCondFailures()
856 { return thread->storeCondFailures; }
858 /** Sets the number of consecutive store conditional failures. */
859 void setStCondFailures(unsigned sc_failures)
860 { thread->storeCondFailures = sc_failures; }
865 BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
866 unsigned size, unsigned flags)
870 Request *sreqLow = NULL;
871 Request *sreqHigh = NULL;
873 if (reqMade && translationStarted) {
875 sreqLow = savedSreqLow;
876 sreqHigh = savedSreqHigh;
878 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
879 thread->contextId(), threadNumber);
881 // Only split the request if the ISA supports unaligned accesses.
882 if (TheISA::HasUnalignedMemAcc) {
883 splitRequest(req, sreqLow, sreqHigh);
885 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
888 if (translationCompleted) {
889 if (fault == NoFault) {
890 effAddr = req->getVaddr();
893 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
895 // Commit will have to clean up whatever happened. Set this
896 // instruction as executed.
900 if (fault != NoFault) {
901 // Return a fixed value to keep simulation deterministic even
902 // along misspeculated paths.
909 traceData->setAddr(addr);
918 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
920 Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
922 data = TheISA::gtoh(data);
925 traceData->setData(data);
933 BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
934 Addr addr, unsigned flags, uint64_t *res)
937 traceData->setAddr(addr);
942 Request *sreqLow = NULL;
943 Request *sreqHigh = NULL;
945 if (reqMade && translationStarted) {
947 sreqLow = savedSreqLow;
948 sreqHigh = savedSreqHigh;
950 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
951 thread->contextId(), threadNumber);
953 // Only split the request if the ISA supports unaligned accesses.
954 if (TheISA::HasUnalignedMemAcc) {
955 splitRequest(req, sreqLow, sreqHigh);
957 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
960 if (fault == NoFault && translationCompleted) {
961 effAddr = req->getVaddr();
964 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
973 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
976 traceData->setData(data);
978 data = TheISA::htog(data);
979 return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
984 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
985 RequestPtr &sreqHigh)
987 // Check to see if the request crosses the next level block boundary.
988 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
989 Addr addr = req->getVaddr();
990 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
991 assert(split_addr <= addr || split_addr - addr < block_size);
994 if (split_addr > addr) {
995 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
1001 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
1002 RequestPtr sreqHigh, uint64_t *res,
1005 translationStarted = true;
1007 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1008 WholeTranslationState *state =
1009 new WholeTranslationState(req, NULL, res, mode);
1011 // One translation if the request isn't split.
1012 DataTranslation<BaseDynInst<Impl> > *trans =
1013 new DataTranslation<BaseDynInst<Impl> >(this, state);
1014 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1015 if (!translationCompleted) {
1016 // Save memory requests.
1017 savedReq = state->mainReq;
1018 savedSreqLow = state->sreqLow;
1019 savedSreqHigh = state->sreqHigh;
1022 WholeTranslationState *state =
1023 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1025 // Two translations when the request is split.
1026 DataTranslation<BaseDynInst<Impl> > *stransLow =
1027 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
1028 DataTranslation<BaseDynInst<Impl> > *stransHigh =
1029 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
1031 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1032 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1033 if (!translationCompleted) {
1034 // Save memory requests.
1035 savedReq = state->mainReq;
1036 savedSreqLow = state->sreqLow;
1037 savedSreqHigh = state->sreqHigh;
1042 template<class Impl>
1044 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1046 fault = state->getFault();
1048 if (state->isUncacheable())
1049 isUncacheable = true;
1051 if (fault == NoFault) {
1052 physEffAddr = state->getPaddr();
1053 memReqFlags = state->getFlags();
1055 if (state->mainReq->isCondSwap()) {
1057 state->mainReq->setExtraData(*state->res);
1061 state->deleteReqs();
1065 translationCompleted = true;
1068 #endif // __CPU_BASE_DYN_INST_HH__