2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * Copyright (c) 2009 The University of Edinburgh
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
52 #include "arch/faults.hh"
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/full_system.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/system.hh"
71 * Defines a dynamic instruction context.
75 class BaseDynInst : public FastAlloc, public RefCounted
78 // Typedef for the CPU.
79 typedef typename Impl::CPUType ImplCPU;
80 typedef typename ImplCPU::ImplState ImplState;
82 // Logical register index type.
83 typedef TheISA::RegIndex RegIndex;
84 // Integer register type.
85 typedef TheISA::IntReg IntReg;
86 // Floating point register type.
87 typedef TheISA::FloatReg FloatReg;
89 // The DynInstPtr type.
90 typedef typename Impl::DynInstPtr DynInstPtr;
91 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
93 // The list of instructions iterator type.
94 typedef typename std::list<DynInstPtr>::iterator ListIt;
97 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
98 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
101 /** The StaticInst used by this BaseDynInst. */
102 StaticInstPtr staticInst;
103 StaticInstPtr macroop;
105 ////////////////////////////////////////////
107 // INSTRUCTION EXECUTION
109 ////////////////////////////////////////////
110 /** InstRecord that tracks this instructions. */
111 Trace::InstRecord *traceData;
113 void demapPage(Addr vaddr, uint64_t asn)
115 cpu->demapPage(vaddr, asn);
117 void demapInstPage(Addr vaddr, uint64_t asn)
119 cpu->demapPage(vaddr, asn);
121 void demapDataPage(Addr vaddr, uint64_t asn)
123 cpu->demapPage(vaddr, asn);
126 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
128 Fault writeMem(uint8_t *data, unsigned size,
129 Addr addr, unsigned flags, uint64_t *res);
131 /** Splits a request in two if it crosses a dcache block. */
132 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
133 RequestPtr &sreqHigh);
135 /** Initiate a DTB address translation. */
136 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
137 RequestPtr sreqHigh, uint64_t *res,
140 /** Finish a DTB address translation. */
141 void finishTranslation(WholeTranslationState *state);
143 /** True if the DTB address translation has started. */
144 bool translationStarted;
146 /** True if the DTB address translation has completed. */
147 bool translationCompleted;
150 * Returns true if the DTB address translation is being delayed due to a hw
153 bool isTranslationDelayed() const
155 return (translationStarted && !translationCompleted);
159 * Saved memory requests (needed when the DTB address translation is
160 * delayed due to a hw page table walk).
163 RequestPtr savedSreqLow;
164 RequestPtr savedSreqHigh;
166 /** @todo: Consider making this private. */
168 /** The sequence number of the instruction. */
172 IqEntry, /// Instruction is in the IQ
173 RobEntry, /// Instruction is in the ROB
174 LsqEntry, /// Instruction is in the LSQ
175 Completed, /// Instruction has completed
176 ResultReady, /// Instruction has its result
177 CanIssue, /// Instruction can issue and execute
178 Issued, /// Instruction has issued
179 Executed, /// Instruction has executed
180 CanCommit, /// Instruction can commit
181 AtCommit, /// Instruction has reached commit
182 Committed, /// Instruction has committed
183 Squashed, /// Instruction is squashed
184 SquashedInIQ, /// Instruction is squashed in the IQ
185 SquashedInLSQ, /// Instruction is squashed in the LSQ
186 SquashedInROB, /// Instruction is squashed in the ROB
187 RecoverInst, /// Is a recover instruction
188 BlockingInst, /// Is a blocking instruction
189 ThreadsyncWait, /// Is a thread synchronization instruction
190 SerializeBefore, /// Needs to serialize on
191 /// instructions ahead of it
192 SerializeAfter, /// Needs to serialize instructions behind it
193 SerializeHandled, /// Serialization has been handled
197 /** The status of this BaseDynInst. Several bits can be set. */
198 std::bitset<NumStatus> status;
200 /** The thread this instruction is from. */
201 ThreadID threadNumber;
203 /** data address space ID, for loads & stores. */
206 /** How many source registers are ready. */
209 /** Pointer to the Impl's CPU object. */
212 /** Pointer to the thread state. */
215 /** The kind of fault this instruction has generated. */
218 /** Pointer to the data for the memory access. */
221 /** The effective virtual address (lds & stores only). */
224 /** The size of the request */
227 /** Is the effective virtual address valid. */
230 /** The effective physical address. */
233 /** The memory request flags (from translation). */
234 unsigned memReqFlags;
242 /** The result of the instruction; assumes for now that there's only one
243 * destination register.
247 /** Records changes to result? */
250 /** Did this instruction execute, or is it predicated false */
254 /** PC state for this instruction. */
257 /** Predicted PC state after this instruction. */
258 TheISA::PCState predPC;
260 /** If this is a branch that was predicted taken */
269 /** Whether or not the source register is ready.
270 * @todo: Not sure this should be here vs the derived class.
272 bool _readySrcRegIdx[MaxInstSrcRegs];
275 /** Flattened register index of the destination registers of this
278 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
280 /** Flattened register index of the source registers of this
283 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
285 /** Physical register index of the destination registers of this
288 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
290 /** Physical register index of the source registers of this
293 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
295 /** Physical register index of the previous producers of the
296 * architected destinations.
298 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
302 /** Returns the physical register index of the i'th destination
305 PhysRegIndex renamedDestRegIdx(int idx) const
307 return _destRegIdx[idx];
310 /** Returns the physical register index of the i'th source register. */
311 PhysRegIndex renamedSrcRegIdx(int idx) const
313 return _srcRegIdx[idx];
316 /** Returns the flattened register index of the i'th destination
319 TheISA::RegIndex flattenedDestRegIdx(int idx) const
321 return _flatDestRegIdx[idx];
324 /** Returns the flattened register index of the i'th source register */
325 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
327 return _flatSrcRegIdx[idx];
330 /** Returns the physical register index of the previous physical register
331 * that remapped to the same logical register index.
333 PhysRegIndex prevDestRegIdx(int idx) const
335 return _prevDestRegIdx[idx];
338 /** Renames a destination register to a physical register. Also records
339 * the previous physical register that the logical register mapped to.
341 void renameDestReg(int idx,
342 PhysRegIndex renamed_dest,
343 PhysRegIndex previous_rename)
345 _destRegIdx[idx] = renamed_dest;
346 _prevDestRegIdx[idx] = previous_rename;
349 /** Renames a source logical register to the physical register which
350 * has/will produce that logical register's result.
351 * @todo: add in whether or not the source register is ready.
353 void renameSrcReg(int idx, PhysRegIndex renamed_src)
355 _srcRegIdx[idx] = renamed_src;
358 /** Flattens a source architectural register index into a logical index.
360 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
362 _flatSrcRegIdx[idx] = flattened_src;
365 /** Flattens a destination architectural register index into a logical
368 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
370 _flatDestRegIdx[idx] = flattened_dest;
372 /** BaseDynInst constructor given a binary instruction.
373 * @param staticInst A StaticInstPtr to the underlying instruction.
374 * @param pc The PC state for the instruction.
375 * @param predPC The predicted next PC state for the instruction.
376 * @param seq_num The sequence number of the instruction.
377 * @param cpu Pointer to the instruction's CPU.
379 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
380 TheISA::PCState pc, TheISA::PCState predPC,
381 InstSeqNum seq_num, ImplCPU *cpu);
383 /** BaseDynInst constructor given a StaticInst pointer.
384 * @param _staticInst The StaticInst for this BaseDynInst.
386 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
388 /** BaseDynInst destructor. */
392 /** Function to initialize variables in the constructors. */
396 /** Dumps out contents of this BaseDynInst. */
399 /** Dumps out contents of this BaseDynInst into given string. */
400 void dump(std::string &outstring);
402 /** Read this CPU's ID. */
403 int cpuId() { return cpu->cpuId(); }
405 /** Read this context's system-wide ID **/
406 int contextId() { return thread->contextId(); }
408 /** Returns the fault type. */
409 Fault getFault() { return fault; }
411 /** Checks whether or not this instruction has had its branch target
412 * calculated yet. For now it is not utilized and is hacked to be
414 * @todo: Actually use this instruction.
416 bool doneTargCalc() { return false; }
418 /** Set the predicted target of this current instruction. */
419 void setPredTarg(const TheISA::PCState &_predPC)
424 const TheISA::PCState &readPredTarg() { return predPC; }
426 /** Returns the predicted PC immediately after the branch. */
427 Addr predInstAddr() { return predPC.instAddr(); }
429 /** Returns the predicted PC two instructions after the branch */
430 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
432 /** Returns the predicted micro PC after the branch */
433 Addr predMicroPC() { return predPC.microPC(); }
435 /** Returns whether the instruction was predicted taken or not. */
441 void setPredTaken(bool predicted_taken)
443 predTaken = predicted_taken;
446 /** Returns whether the instruction mispredicted. */
449 TheISA::PCState tempPC = pc;
450 TheISA::advancePC(tempPC, staticInst);
451 return !(tempPC == predPC);
455 // Instruction types. Forward checks to StaticInst object.
457 bool isNop() const { return staticInst->isNop(); }
458 bool isMemRef() const { return staticInst->isMemRef(); }
459 bool isLoad() const { return staticInst->isLoad(); }
460 bool isStore() const { return staticInst->isStore(); }
461 bool isStoreConditional() const
462 { return staticInst->isStoreConditional(); }
463 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
464 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
465 bool isInteger() const { return staticInst->isInteger(); }
466 bool isFloating() const { return staticInst->isFloating(); }
467 bool isControl() const { return staticInst->isControl(); }
468 bool isCall() const { return staticInst->isCall(); }
469 bool isReturn() const { return staticInst->isReturn(); }
470 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
471 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
472 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
473 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
474 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
475 bool isThreadSync() const { return staticInst->isThreadSync(); }
476 bool isSerializing() const { return staticInst->isSerializing(); }
477 bool isSerializeBefore() const
478 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
479 bool isSerializeAfter() const
480 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
481 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
482 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
483 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
484 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
485 bool isQuiesce() const { return staticInst->isQuiesce(); }
486 bool isIprAccess() const { return staticInst->isIprAccess(); }
487 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
488 bool isSyscall() const { return staticInst->isSyscall(); }
489 bool isMacroop() const { return staticInst->isMacroop(); }
490 bool isMicroop() const { return staticInst->isMicroop(); }
491 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
492 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
493 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
494 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
496 /** Temporarily sets this instruction as a serialize before instruction. */
497 void setSerializeBefore() { status.set(SerializeBefore); }
499 /** Clears the serializeBefore part of this instruction. */
500 void clearSerializeBefore() { status.reset(SerializeBefore); }
502 /** Checks if this serializeBefore is only temporarily set. */
503 bool isTempSerializeBefore() { return status[SerializeBefore]; }
505 /** Temporarily sets this instruction as a serialize after instruction. */
506 void setSerializeAfter() { status.set(SerializeAfter); }
508 /** Clears the serializeAfter part of this instruction.*/
509 void clearSerializeAfter() { status.reset(SerializeAfter); }
511 /** Checks if this serializeAfter is only temporarily set. */
512 bool isTempSerializeAfter() { return status[SerializeAfter]; }
514 /** Sets the serialization part of this instruction as handled. */
515 void setSerializeHandled() { status.set(SerializeHandled); }
517 /** Checks if the serialization part of this instruction has been
518 * handled. This does not apply to the temporary serializing
519 * state; it only applies to this instruction's own permanent
522 bool isSerializeHandled() { return status[SerializeHandled]; }
524 /** Returns the opclass of this instruction. */
525 OpClass opClass() const { return staticInst->opClass(); }
527 /** Returns the branch target address. */
528 TheISA::PCState branchTarget() const
529 { return staticInst->branchTarget(pc); }
531 /** Returns the number of source registers. */
532 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
534 /** Returns the number of destination registers. */
535 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
537 // the following are used to track physical register usage
538 // for machines with separate int & FP reg files
539 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
540 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
542 /** Returns the logical register index of the i'th destination register. */
543 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
545 /** Returns the logical register index of the i'th source register. */
546 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
548 /** Returns the result of an integer instruction. */
549 uint64_t readIntResult() { return instResult.integer; }
551 /** Returns the result of a floating point instruction. */
552 float readFloatResult() { return (float)instResult.dbl; }
554 /** Returns the result of a floating point (double) instruction. */
555 double readDoubleResult() { return instResult.dbl; }
557 /** Records an integer register being set to a value. */
558 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
561 instResult.integer = val;
564 /** Records an fp register being set to a value. */
565 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
570 instResult.dbl = (double)val;
571 else if (width == 64)
572 instResult.dbl = val;
574 panic("Unsupported width!");
578 /** Records an fp register being set to a value. */
579 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
582 instResult.dbl = (double)val;
585 /** Records an fp register being set to an integer value. */
586 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
590 instResult.integer = val;
593 /** Records an fp register being set to an integer value. */
594 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
597 instResult.integer = val;
600 /** Records that one of the source registers is ready. */
601 void markSrcRegReady();
603 /** Marks a specific register as ready. */
604 void markSrcRegReady(RegIndex src_idx);
606 /** Returns if a source register is ready. */
607 bool isReadySrcRegIdx(int idx) const
609 return this->_readySrcRegIdx[idx];
612 /** Sets this instruction as completed. */
613 void setCompleted() { status.set(Completed); }
615 /** Returns whether or not this instruction is completed. */
616 bool isCompleted() const { return status[Completed]; }
618 /** Marks the result as ready. */
619 void setResultReady() { status.set(ResultReady); }
621 /** Returns whether or not the result is ready. */
622 bool isResultReady() const { return status[ResultReady]; }
624 /** Sets this instruction as ready to issue. */
625 void setCanIssue() { status.set(CanIssue); }
627 /** Returns whether or not this instruction is ready to issue. */
628 bool readyToIssue() const { return status[CanIssue]; }
630 /** Clears this instruction being able to issue. */
631 void clearCanIssue() { status.reset(CanIssue); }
633 /** Sets this instruction as issued from the IQ. */
634 void setIssued() { status.set(Issued); }
636 /** Returns whether or not this instruction has issued. */
637 bool isIssued() const { return status[Issued]; }
639 /** Clears this instruction as being issued. */
640 void clearIssued() { status.reset(Issued); }
642 /** Sets this instruction as executed. */
643 void setExecuted() { status.set(Executed); }
645 /** Returns whether or not this instruction has executed. */
646 bool isExecuted() const { return status[Executed]; }
648 /** Sets this instruction as ready to commit. */
649 void setCanCommit() { status.set(CanCommit); }
651 /** Clears this instruction as being ready to commit. */
652 void clearCanCommit() { status.reset(CanCommit); }
654 /** Returns whether or not this instruction is ready to commit. */
655 bool readyToCommit() const { return status[CanCommit]; }
657 void setAtCommit() { status.set(AtCommit); }
659 bool isAtCommit() { return status[AtCommit]; }
661 /** Sets this instruction as committed. */
662 void setCommitted() { status.set(Committed); }
664 /** Returns whether or not this instruction is committed. */
665 bool isCommitted() const { return status[Committed]; }
667 /** Sets this instruction as squashed. */
668 void setSquashed() { status.set(Squashed); }
670 /** Returns whether or not this instruction is squashed. */
671 bool isSquashed() const { return status[Squashed]; }
673 //Instruction Queue Entry
674 //-----------------------
675 /** Sets this instruction as a entry the IQ. */
676 void setInIQ() { status.set(IqEntry); }
678 /** Sets this instruction as a entry the IQ. */
679 void clearInIQ() { status.reset(IqEntry); }
681 /** Returns whether or not this instruction has issued. */
682 bool isInIQ() const { return status[IqEntry]; }
684 /** Sets this instruction as squashed in the IQ. */
685 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
687 /** Returns whether or not this instruction is squashed in the IQ. */
688 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
691 //Load / Store Queue Functions
692 //-----------------------
693 /** Sets this instruction as a entry the LSQ. */
694 void setInLSQ() { status.set(LsqEntry); }
696 /** Sets this instruction as a entry the LSQ. */
697 void removeInLSQ() { status.reset(LsqEntry); }
699 /** Returns whether or not this instruction is in the LSQ. */
700 bool isInLSQ() const { return status[LsqEntry]; }
702 /** Sets this instruction as squashed in the LSQ. */
703 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
705 /** Returns whether or not this instruction is squashed in the LSQ. */
706 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
709 //Reorder Buffer Functions
710 //-----------------------
711 /** Sets this instruction as a entry the ROB. */
712 void setInROB() { status.set(RobEntry); }
714 /** Sets this instruction as a entry the ROB. */
715 void clearInROB() { status.reset(RobEntry); }
717 /** Returns whether or not this instruction is in the ROB. */
718 bool isInROB() const { return status[RobEntry]; }
720 /** Sets this instruction as squashed in the ROB. */
721 void setSquashedInROB() { status.set(SquashedInROB); }
723 /** Returns whether or not this instruction is squashed in the ROB. */
724 bool isSquashedInROB() const { return status[SquashedInROB]; }
726 /** Read the PC state of this instruction. */
727 const TheISA::PCState pcState() const { return pc; }
729 /** Set the PC state of this instruction. */
730 const void pcState(const TheISA::PCState &val) { pc = val; }
732 /** Read the PC of this instruction. */
733 const Addr instAddr() const { return pc.instAddr(); }
735 /** Read the PC of the next instruction. */
736 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
738 /**Read the micro PC of this instruction. */
739 const Addr microPC() const { return pc.microPC(); }
746 void setPredicate(bool val)
751 traceData->setPredicate(val);
755 /** Sets the ASID. */
756 void setASID(short addr_space_id) { asid = addr_space_id; }
758 /** Sets the thread id. */
759 void setTid(ThreadID tid) { threadNumber = tid; }
761 /** Sets the pointer to the thread state. */
762 void setThreadState(ImplState *state) { thread = state; }
764 /** Returns the thread context. */
765 ThreadContext *tcBase() { return thread->getTC(); }
768 /** Instruction effective address.
769 * @todo: Consider if this is necessary or not.
773 /** Whether or not the effective address calculation is completed.
774 * @todo: Consider if this is necessary or not.
778 /** Is this instruction's memory access uncacheable. */
781 /** Has this instruction generated a memory request. */
785 /** Sets the effective address. */
786 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
788 /** Returns the effective address. */
789 const Addr &getEA() const { return instEffAddr; }
791 /** Returns whether or not the eff. addr. calculation has been completed. */
792 bool doneEACalc() { return eaCalcDone; }
794 /** Returns whether or not the eff. addr. source registers are ready. */
797 /** Whether or not the memory operation is done. */
800 /** Is this instruction's memory access uncacheable. */
801 bool uncacheable() { return isUncacheable; }
803 /** Has this instruction generated a memory request. */
804 bool hasRequest() { return reqMade; }
807 /** Load queue index. */
810 /** Store queue index. */
813 /** Iterator pointing to this BaseDynInst in the list of all insts. */
816 /** Returns iterator to this instruction in the list of all insts. */
817 ListIt &getInstListIt() { return instListIt; }
819 /** Sets iterator for this instruction in the list of all insts. */
820 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
823 /** Returns the number of consecutive store conditional failures. */
824 unsigned readStCondFailures()
825 { return thread->storeCondFailures; }
827 /** Sets the number of consecutive store conditional failures. */
828 void setStCondFailures(unsigned sc_failures)
829 { thread->storeCondFailures = sc_failures; }
834 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
835 unsigned size, unsigned flags)
839 Request *sreqLow = NULL;
840 Request *sreqHigh = NULL;
842 if (reqMade && translationStarted) {
844 sreqLow = savedSreqLow;
845 sreqHigh = savedSreqHigh;
847 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
848 thread->contextId(), threadNumber);
850 // Only split the request if the ISA supports unaligned accesses.
851 if (TheISA::HasUnalignedMemAcc) {
852 splitRequest(req, sreqLow, sreqHigh);
854 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
857 if (translationCompleted) {
858 if (fault == NoFault) {
859 effAddr = req->getVaddr();
862 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
864 // Commit will have to clean up whatever happened. Set this
865 // instruction as executed.
869 if (fault != NoFault) {
870 // Return a fixed value to keep simulation deterministic even
871 // along misspeculated paths.
878 traceData->setAddr(addr);
886 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
887 Addr addr, unsigned flags, uint64_t *res)
890 traceData->setAddr(addr);
895 Request *sreqLow = NULL;
896 Request *sreqHigh = NULL;
898 if (reqMade && translationStarted) {
900 sreqLow = savedSreqLow;
901 sreqHigh = savedSreqHigh;
903 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
904 thread->contextId(), threadNumber);
906 // Only split the request if the ISA supports unaligned accesses.
907 if (TheISA::HasUnalignedMemAcc) {
908 splitRequest(req, sreqLow, sreqHigh);
910 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
913 if (fault == NoFault && translationCompleted) {
914 effAddr = req->getVaddr();
917 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
925 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
926 RequestPtr &sreqHigh)
928 // Check to see if the request crosses the next level block boundary.
929 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
930 Addr addr = req->getVaddr();
931 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
932 assert(split_addr <= addr || split_addr - addr < block_size);
935 if (split_addr > addr) {
936 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
942 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
943 RequestPtr sreqHigh, uint64_t *res,
946 translationStarted = true;
948 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
949 WholeTranslationState *state =
950 new WholeTranslationState(req, NULL, res, mode);
952 // One translation if the request isn't split.
953 DataTranslation<BaseDynInstPtr> *trans =
954 new DataTranslation<BaseDynInstPtr>(this, state);
955 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
956 if (!translationCompleted) {
957 // Save memory requests.
958 savedReq = state->mainReq;
959 savedSreqLow = state->sreqLow;
960 savedSreqHigh = state->sreqHigh;
963 WholeTranslationState *state =
964 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
966 // Two translations when the request is split.
967 DataTranslation<BaseDynInstPtr> *stransLow =
968 new DataTranslation<BaseDynInstPtr>(this, state, 0);
969 DataTranslation<BaseDynInstPtr> *stransHigh =
970 new DataTranslation<BaseDynInstPtr>(this, state, 1);
972 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
973 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
974 if (!translationCompleted) {
975 // Save memory requests.
976 savedReq = state->mainReq;
977 savedSreqLow = state->sreqLow;
978 savedSreqHigh = state->sreqHigh;
985 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
987 fault = state->getFault();
989 if (state->isUncacheable())
990 isUncacheable = true;
992 if (fault == NoFault) {
993 physEffAddr = state->getPaddr();
994 memReqFlags = state->getFlags();
996 if (state->mainReq->isCondSwap()) {
998 state->mainReq->setExtraData(*state->res);
1002 state->deleteReqs();
1006 translationCompleted = true;
1009 #endif // __CPU_BASE_DYN_INST_HH__