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46 #ifndef __CPU_BASE_DYN_INST_HH__
47 #define __CPU_BASE_DYN_INST_HH__
55 #include "arch/generic/tlb.hh"
56 #include "arch/utility.hh"
57 #include "base/trace.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/checker/cpu.hh"
60 #include "cpu/o3/comm.hh"
61 #include "cpu/exec_context.hh"
62 #include "cpu/exetrace.hh"
63 #include "cpu/inst_seq.hh"
64 #include "cpu/op_class.hh"
65 #include "cpu/static_inst.hh"
66 #include "cpu/translation.hh"
67 #include "mem/packet.hh"
68 #include "mem/request.hh"
69 #include "sim/byteswap.hh"
70 #include "sim/system.hh"
74 * Defines a dynamic instruction context.
78 class BaseDynInst : public ExecContext, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
88 // The DynInstPtr type.
89 typedef typename Impl::DynInstPtr DynInstPtr;
90 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
92 // The list of instructions iterator type.
93 typedef typename std::list<DynInstPtr>::iterator ListIt;
96 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
97 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
103 void set(uint64_t i) { integer = i; }
104 void set(double d) { dbl = d; }
105 void get(uint64_t& i) { i = integer; }
106 void get(double& d) { d = dbl; }
111 IqEntry, /// Instruction is in the IQ
112 RobEntry, /// Instruction is in the ROB
113 LsqEntry, /// Instruction is in the LSQ
114 Completed, /// Instruction has completed
115 ResultReady, /// Instruction has its result
116 CanIssue, /// Instruction can issue and execute
117 Issued, /// Instruction has issued
118 Executed, /// Instruction has executed
119 CanCommit, /// Instruction can commit
120 AtCommit, /// Instruction has reached commit
121 Committed, /// Instruction has committed
122 Squashed, /// Instruction is squashed
123 SquashedInIQ, /// Instruction is squashed in the IQ
124 SquashedInLSQ, /// Instruction is squashed in the LSQ
125 SquashedInROB, /// Instruction is squashed in the ROB
126 RecoverInst, /// Is a recover instruction
127 BlockingInst, /// Is a blocking instruction
128 ThreadsyncWait, /// Is a thread synchronization instruction
129 SerializeBefore, /// Needs to serialize on
130 /// instructions ahead of it
131 SerializeAfter, /// Needs to serialize instructions behind it
132 SerializeHandled, /// Serialization has been handled
138 TranslationCompleted,
139 PossibleLoadViolation,
145 /** Whether or not the effective address calculation is completed.
146 * @todo: Consider if this is necessary or not.
156 /** The sequence number of the instruction. */
159 /** The StaticInst used by this BaseDynInst. */
160 const StaticInstPtr staticInst;
162 /** Pointer to the Impl's CPU object. */
165 BaseCPU *getCpuPtr() { return cpu; }
167 /** Pointer to the thread state. */
170 /** The kind of fault this instruction has generated. */
173 /** InstRecord that tracks this instructions. */
174 Trace::InstRecord *traceData;
177 /** The result of the instruction; assumes an instruction can have many
178 * destination registers.
180 std::queue<Result> instResult;
182 /** PC state for this instruction. */
185 /* An amalgamation of a lot of boolean values into one */
186 std::bitset<MaxFlags> instFlags;
188 /** The status of this BaseDynInst. Several bits can be set. */
189 std::bitset<NumStatus> status;
191 /** Whether or not the source register is ready.
192 * @todo: Not sure this should be here vs the derived class.
194 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
197 /** The thread this instruction is from. */
198 ThreadID threadNumber;
200 /** Iterator pointing to this BaseDynInst in the list of all insts. */
203 ////////////////////// Branch Data ///////////////
204 /** Predicted PC state after this instruction. */
205 TheISA::PCState predPC;
207 /** The Macroop if one exists */
208 const StaticInstPtr macroop;
210 /** How many source registers are ready. */
214 /////////////////////// Load Store Data //////////////////////
215 /** The effective virtual address (lds & stores only). */
218 /** The effective physical address. */
221 /** The effective physical address
222 * of the second request for a split request
224 Addr physEffAddrHigh;
226 /** The memory request flags (from translation). */
227 unsigned memReqFlags;
229 /** data address space ID, for loads & stores. */
232 /** The size of the request */
235 /** Pointer to the data for the memory access. */
238 /** Load queue index. */
241 /** Store queue index. */
245 /////////////////////// TLB Miss //////////////////////
247 * Saved memory requests (needed when the DTB address translation is
248 * delayed due to a hw page table walk).
251 RequestPtr savedSreqLow;
252 RequestPtr savedSreqHigh;
254 /////////////////////// Checker //////////////////////
255 // Need a copy of main request pointer to verify on writes.
256 RequestPtr reqToVerify;
259 /** Instruction effective address.
260 * @todo: Consider if this is necessary or not.
265 /** Flattened register index of the destination registers of this
268 std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx;
270 /** Physical register index of the destination registers of this
273 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx;
275 /** Physical register index of the source registers of this
278 std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx;
280 /** Physical register index of the previous producers of the
281 * architected destinations.
283 std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx;
287 /** Records changes to result? */
288 void recordResult(bool f) { instFlags[RecordResult] = f; }
290 /** Is the effective virtual address valid. */
291 bool effAddrValid() const { return instFlags[EffAddrValid]; }
293 /** Whether or not the memory operation is done. */
294 bool memOpDone() const { return instFlags[MemOpDone]; }
295 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
298 ////////////////////////////////////////////
300 // INSTRUCTION EXECUTION
302 ////////////////////////////////////////////
304 void demapPage(Addr vaddr, uint64_t asn)
306 cpu->demapPage(vaddr, asn);
308 void demapInstPage(Addr vaddr, uint64_t asn)
310 cpu->demapPage(vaddr, asn);
312 void demapDataPage(Addr vaddr, uint64_t asn)
314 cpu->demapPage(vaddr, asn);
317 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
319 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
320 Request::Flags flags, uint64_t *res);
322 /** Splits a request in two if it crosses a dcache block. */
323 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
324 RequestPtr &sreqHigh);
326 /** Initiate a DTB address translation. */
327 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
328 RequestPtr sreqHigh, uint64_t *res,
331 /** Finish a DTB address translation. */
332 void finishTranslation(WholeTranslationState *state);
334 /** True if the DTB address translation has started. */
335 bool translationStarted() const { return instFlags[TranslationStarted]; }
336 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
338 /** True if the DTB address translation has completed. */
339 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
340 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
342 /** True if this address was found to match a previous load and they issued
343 * out of order. If that happend, then it's only a problem if an incoming
344 * snoop invalidate modifies the line, in which case we need to squash.
345 * If nothing modified the line the order doesn't matter.
347 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
348 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
350 /** True if the address hit a external snoop while sitting in the LSQ.
351 * If this is true and a older instruction sees it, this instruction must
354 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
355 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
358 * Returns true if the DTB address translation is being delayed due to a hw
361 bool isTranslationDelayed() const
363 return (translationStarted() && !translationCompleted());
371 /** Returns the physical register index of the i'th destination
374 PhysRegIndex renamedDestRegIdx(int idx) const
376 return _destRegIdx[idx];
379 /** Returns the physical register index of the i'th source register. */
380 PhysRegIndex renamedSrcRegIdx(int idx) const
382 assert(TheISA::MaxInstSrcRegs > idx);
383 return _srcRegIdx[idx];
386 /** Returns the flattened register index of the i'th destination
389 TheISA::RegIndex flattenedDestRegIdx(int idx) const
391 return _flatDestRegIdx[idx];
394 /** Returns the physical register index of the previous physical register
395 * that remapped to the same logical register index.
397 PhysRegIndex prevDestRegIdx(int idx) const
399 return _prevDestRegIdx[idx];
402 /** Renames a destination register to a physical register. Also records
403 * the previous physical register that the logical register mapped to.
405 void renameDestReg(int idx,
406 PhysRegIndex renamed_dest,
407 PhysRegIndex previous_rename)
409 _destRegIdx[idx] = renamed_dest;
410 _prevDestRegIdx[idx] = previous_rename;
413 /** Renames a source logical register to the physical register which
414 * has/will produce that logical register's result.
415 * @todo: add in whether or not the source register is ready.
417 void renameSrcReg(int idx, PhysRegIndex renamed_src)
419 _srcRegIdx[idx] = renamed_src;
422 /** Flattens a destination architectural register index into a logical
425 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
427 _flatDestRegIdx[idx] = flattened_dest;
429 /** BaseDynInst constructor given a binary instruction.
430 * @param staticInst A StaticInstPtr to the underlying instruction.
431 * @param pc The PC state for the instruction.
432 * @param predPC The predicted next PC state for the instruction.
433 * @param seq_num The sequence number of the instruction.
434 * @param cpu Pointer to the instruction's CPU.
436 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
437 TheISA::PCState pc, TheISA::PCState predPC,
438 InstSeqNum seq_num, ImplCPU *cpu);
440 /** BaseDynInst constructor given a StaticInst pointer.
441 * @param _staticInst The StaticInst for this BaseDynInst.
443 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
445 /** BaseDynInst destructor. */
449 /** Function to initialize variables in the constructors. */
453 /** Dumps out contents of this BaseDynInst. */
456 /** Dumps out contents of this BaseDynInst into given string. */
457 void dump(std::string &outstring);
459 /** Read this CPU's ID. */
460 int cpuId() const { return cpu->cpuId(); }
462 /** Read this CPU's Socket ID. */
463 uint32_t socketId() const { return cpu->socketId(); }
465 /** Read this CPU's data requestor ID */
466 MasterID masterId() const { return cpu->dataMasterId(); }
468 /** Read this context's system-wide ID **/
469 ContextID contextId() const { return thread->contextId(); }
471 /** Returns the fault type. */
472 Fault getFault() const { return fault; }
474 /** Checks whether or not this instruction has had its branch target
475 * calculated yet. For now it is not utilized and is hacked to be
477 * @todo: Actually use this instruction.
479 bool doneTargCalc() { return false; }
481 /** Set the predicted target of this current instruction. */
482 void setPredTarg(const TheISA::PCState &_predPC)
487 const TheISA::PCState &readPredTarg() { return predPC; }
489 /** Returns the predicted PC immediately after the branch. */
490 Addr predInstAddr() { return predPC.instAddr(); }
492 /** Returns the predicted PC two instructions after the branch */
493 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
495 /** Returns the predicted micro PC after the branch */
496 Addr predMicroPC() { return predPC.microPC(); }
498 /** Returns whether the instruction was predicted taken or not. */
501 return instFlags[PredTaken];
504 void setPredTaken(bool predicted_taken)
506 instFlags[PredTaken] = predicted_taken;
509 /** Returns whether the instruction mispredicted. */
512 TheISA::PCState tempPC = pc;
513 TheISA::advancePC(tempPC, staticInst);
514 return !(tempPC == predPC);
518 // Instruction types. Forward checks to StaticInst object.
520 bool isNop() const { return staticInst->isNop(); }
521 bool isMemRef() const { return staticInst->isMemRef(); }
522 bool isLoad() const { return staticInst->isLoad(); }
523 bool isStore() const { return staticInst->isStore(); }
524 bool isStoreConditional() const
525 { return staticInst->isStoreConditional(); }
526 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
527 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
528 bool isInteger() const { return staticInst->isInteger(); }
529 bool isFloating() const { return staticInst->isFloating(); }
530 bool isControl() const { return staticInst->isControl(); }
531 bool isCall() const { return staticInst->isCall(); }
532 bool isReturn() const { return staticInst->isReturn(); }
533 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
534 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
535 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
536 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
537 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
538 bool isThreadSync() const { return staticInst->isThreadSync(); }
539 bool isSerializing() const { return staticInst->isSerializing(); }
540 bool isSerializeBefore() const
541 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
542 bool isSerializeAfter() const
543 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
544 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
545 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
546 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
547 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
548 bool isQuiesce() const { return staticInst->isQuiesce(); }
549 bool isIprAccess() const { return staticInst->isIprAccess(); }
550 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
551 bool isSyscall() const { return staticInst->isSyscall(); }
552 bool isMacroop() const { return staticInst->isMacroop(); }
553 bool isMicroop() const { return staticInst->isMicroop(); }
554 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
555 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
556 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
557 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
559 /** Temporarily sets this instruction as a serialize before instruction. */
560 void setSerializeBefore() { status.set(SerializeBefore); }
562 /** Clears the serializeBefore part of this instruction. */
563 void clearSerializeBefore() { status.reset(SerializeBefore); }
565 /** Checks if this serializeBefore is only temporarily set. */
566 bool isTempSerializeBefore() { return status[SerializeBefore]; }
568 /** Temporarily sets this instruction as a serialize after instruction. */
569 void setSerializeAfter() { status.set(SerializeAfter); }
571 /** Clears the serializeAfter part of this instruction.*/
572 void clearSerializeAfter() { status.reset(SerializeAfter); }
574 /** Checks if this serializeAfter is only temporarily set. */
575 bool isTempSerializeAfter() { return status[SerializeAfter]; }
577 /** Sets the serialization part of this instruction as handled. */
578 void setSerializeHandled() { status.set(SerializeHandled); }
580 /** Checks if the serialization part of this instruction has been
581 * handled. This does not apply to the temporary serializing
582 * state; it only applies to this instruction's own permanent
585 bool isSerializeHandled() { return status[SerializeHandled]; }
587 /** Returns the opclass of this instruction. */
588 OpClass opClass() const { return staticInst->opClass(); }
590 /** Returns the branch target address. */
591 TheISA::PCState branchTarget() const
592 { return staticInst->branchTarget(pc); }
594 /** Returns the number of source registers. */
595 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
597 /** Returns the number of destination registers. */
598 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
600 // the following are used to track physical register usage
601 // for machines with separate int & FP reg files
602 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
603 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
604 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
606 /** Returns the logical register index of the i'th destination register. */
607 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
609 /** Returns the logical register index of the i'th source register. */
610 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
612 /** Pops a result off the instResult queue */
616 if (!instResult.empty()) {
617 instResult.front().get(t);
622 /** Read the most recent result stored by this instruction */
624 void readResult(T& t)
626 instResult.back().get(t);
629 /** Pushes a result onto the instResult queue */
633 if (instFlags[RecordResult]) {
636 instResult.push(instRes);
640 /** Records an integer register being set to a value. */
641 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
643 setResult<uint64_t>(val);
646 /** Records a CC register being set to a value. */
647 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
649 setResult<uint64_t>(val);
652 /** Records an fp register being set to a value. */
653 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
655 setResult<double>(val);
658 /** Records an fp register being set to an integer value. */
659 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
661 setResult<uint64_t>(val);
664 /** Records that one of the source registers is ready. */
665 void markSrcRegReady();
667 /** Marks a specific register as ready. */
668 void markSrcRegReady(RegIndex src_idx);
670 /** Returns if a source register is ready. */
671 bool isReadySrcRegIdx(int idx) const
673 return this->_readySrcRegIdx[idx];
676 /** Sets this instruction as completed. */
677 void setCompleted() { status.set(Completed); }
679 /** Returns whether or not this instruction is completed. */
680 bool isCompleted() const { return status[Completed]; }
682 /** Marks the result as ready. */
683 void setResultReady() { status.set(ResultReady); }
685 /** Returns whether or not the result is ready. */
686 bool isResultReady() const { return status[ResultReady]; }
688 /** Sets this instruction as ready to issue. */
689 void setCanIssue() { status.set(CanIssue); }
691 /** Returns whether or not this instruction is ready to issue. */
692 bool readyToIssue() const { return status[CanIssue]; }
694 /** Clears this instruction being able to issue. */
695 void clearCanIssue() { status.reset(CanIssue); }
697 /** Sets this instruction as issued from the IQ. */
698 void setIssued() { status.set(Issued); }
700 /** Returns whether or not this instruction has issued. */
701 bool isIssued() const { return status[Issued]; }
703 /** Clears this instruction as being issued. */
704 void clearIssued() { status.reset(Issued); }
706 /** Sets this instruction as executed. */
707 void setExecuted() { status.set(Executed); }
709 /** Returns whether or not this instruction has executed. */
710 bool isExecuted() const { return status[Executed]; }
712 /** Sets this instruction as ready to commit. */
713 void setCanCommit() { status.set(CanCommit); }
715 /** Clears this instruction as being ready to commit. */
716 void clearCanCommit() { status.reset(CanCommit); }
718 /** Returns whether or not this instruction is ready to commit. */
719 bool readyToCommit() const { return status[CanCommit]; }
721 void setAtCommit() { status.set(AtCommit); }
723 bool isAtCommit() { return status[AtCommit]; }
725 /** Sets this instruction as committed. */
726 void setCommitted() { status.set(Committed); }
728 /** Returns whether or not this instruction is committed. */
729 bool isCommitted() const { return status[Committed]; }
731 /** Sets this instruction as squashed. */
732 void setSquashed() { status.set(Squashed); }
734 /** Returns whether or not this instruction is squashed. */
735 bool isSquashed() const { return status[Squashed]; }
737 //Instruction Queue Entry
738 //-----------------------
739 /** Sets this instruction as a entry the IQ. */
740 void setInIQ() { status.set(IqEntry); }
742 /** Sets this instruction as a entry the IQ. */
743 void clearInIQ() { status.reset(IqEntry); }
745 /** Returns whether or not this instruction has issued. */
746 bool isInIQ() const { return status[IqEntry]; }
748 /** Sets this instruction as squashed in the IQ. */
749 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
751 /** Returns whether or not this instruction is squashed in the IQ. */
752 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
755 //Load / Store Queue Functions
756 //-----------------------
757 /** Sets this instruction as a entry the LSQ. */
758 void setInLSQ() { status.set(LsqEntry); }
760 /** Sets this instruction as a entry the LSQ. */
761 void removeInLSQ() { status.reset(LsqEntry); }
763 /** Returns whether or not this instruction is in the LSQ. */
764 bool isInLSQ() const { return status[LsqEntry]; }
766 /** Sets this instruction as squashed in the LSQ. */
767 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
769 /** Returns whether or not this instruction is squashed in the LSQ. */
770 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
773 //Reorder Buffer Functions
774 //-----------------------
775 /** Sets this instruction as a entry the ROB. */
776 void setInROB() { status.set(RobEntry); }
778 /** Sets this instruction as a entry the ROB. */
779 void clearInROB() { status.reset(RobEntry); }
781 /** Returns whether or not this instruction is in the ROB. */
782 bool isInROB() const { return status[RobEntry]; }
784 /** Sets this instruction as squashed in the ROB. */
785 void setSquashedInROB() { status.set(SquashedInROB); }
787 /** Returns whether or not this instruction is squashed in the ROB. */
788 bool isSquashedInROB() const { return status[SquashedInROB]; }
790 /** Read the PC state of this instruction. */
791 TheISA::PCState pcState() const { return pc; }
793 /** Set the PC state of this instruction. */
794 void pcState(const TheISA::PCState &val) { pc = val; }
796 /** Read the PC of this instruction. */
797 Addr instAddr() const { return pc.instAddr(); }
799 /** Read the PC of the next instruction. */
800 Addr nextInstAddr() const { return pc.nextInstAddr(); }
802 /**Read the micro PC of this instruction. */
803 Addr microPC() const { return pc.microPC(); }
807 return instFlags[Predicate];
810 void setPredicate(bool val)
812 instFlags[Predicate] = val;
815 traceData->setPredicate(val);
819 /** Sets the ASID. */
820 void setASID(short addr_space_id) { asid = addr_space_id; }
822 /** Sets the thread id. */
823 void setTid(ThreadID tid) { threadNumber = tid; }
825 /** Sets the pointer to the thread state. */
826 void setThreadState(ImplState *state) { thread = state; }
828 /** Returns the thread context. */
829 ThreadContext *tcBase() { return thread->getTC(); }
832 /** Sets the effective address. */
833 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
835 /** Returns the effective address. */
836 Addr getEA() const { return instEffAddr; }
838 /** Returns whether or not the eff. addr. calculation has been completed. */
839 bool doneEACalc() { return instFlags[EACalcDone]; }
841 /** Returns whether or not the eff. addr. source registers are ready. */
844 /** Is this instruction's memory access strictly ordered? */
845 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
847 /** Has this instruction generated a memory request. */
848 bool hasRequest() { return instFlags[ReqMade]; }
850 /** Returns iterator to this instruction in the list of all insts. */
851 ListIt &getInstListIt() { return instListIt; }
853 /** Sets iterator for this instruction in the list of all insts. */
854 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
857 /** Returns the number of consecutive store conditional failures. */
858 unsigned int readStCondFailures() const
859 { return thread->storeCondFailures; }
861 /** Sets the number of consecutive store conditional failures. */
862 void setStCondFailures(unsigned int sc_failures)
863 { thread->storeCondFailures = sc_failures; }
866 // monitor/mwait funtions
867 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
868 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
869 void mwaitAtomic(ThreadContext *tc)
870 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
871 AddressMonitor *getAddrMonitor()
872 { return cpu->getCpuAddrMonitor(threadNumber); }
877 BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
878 Request::Flags flags)
880 instFlags[ReqMade] = true;
882 Request *sreqLow = NULL;
883 Request *sreqHigh = NULL;
885 if (instFlags[ReqMade] && translationStarted()) {
887 sreqLow = savedSreqLow;
888 sreqHigh = savedSreqHigh;
890 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
891 thread->contextId());
893 req->taskId(cpu->taskId());
895 // Only split the request if the ISA supports unaligned accesses.
896 if (TheISA::HasUnalignedMemAcc) {
897 splitRequest(req, sreqLow, sreqHigh);
899 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
902 if (translationCompleted()) {
903 if (fault == NoFault) {
904 effAddr = req->getVaddr();
906 instFlags[EffAddrValid] = true;
909 if (reqToVerify != NULL) {
912 reqToVerify = new Request(*req);
914 fault = cpu->read(req, sreqLow, sreqHigh, lqIdx);
916 // Commit will have to clean up whatever happened. Set this
917 // instruction as executed.
923 traceData->setMem(addr, size, flags);
930 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
931 Request::Flags flags, uint64_t *res)
934 traceData->setMem(addr, size, flags);
936 instFlags[ReqMade] = true;
938 Request *sreqLow = NULL;
939 Request *sreqHigh = NULL;
941 if (instFlags[ReqMade] && translationStarted()) {
943 sreqLow = savedSreqLow;
944 sreqHigh = savedSreqHigh;
946 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
947 thread->contextId());
949 req->taskId(cpu->taskId());
951 // Only split the request if the ISA supports unaligned accesses.
952 if (TheISA::HasUnalignedMemAcc) {
953 splitRequest(req, sreqLow, sreqHigh);
955 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
958 if (fault == NoFault && translationCompleted()) {
959 effAddr = req->getVaddr();
961 instFlags[EffAddrValid] = true;
964 if (reqToVerify != NULL) {
967 reqToVerify = new Request(*req);
969 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
977 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
978 RequestPtr &sreqHigh)
980 // Check to see if the request crosses the next level block boundary.
981 unsigned block_size = cpu->cacheLineSize();
982 Addr addr = req->getVaddr();
983 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
984 assert(split_addr <= addr || split_addr - addr < block_size);
987 if (split_addr > addr) {
988 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
994 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
995 RequestPtr sreqHigh, uint64_t *res,
998 translationStarted(true);
1000 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
1001 WholeTranslationState *state =
1002 new WholeTranslationState(req, NULL, res, mode);
1004 // One translation if the request isn't split.
1005 DataTranslation<BaseDynInstPtr> *trans =
1006 new DataTranslation<BaseDynInstPtr>(this, state);
1008 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1010 if (!translationCompleted()) {
1011 // The translation isn't yet complete, so we can't possibly have a
1012 // fault. Overwrite any existing fault we might have from a previous
1013 // execution of this instruction (e.g. an uncachable load that
1014 // couldn't execute because it wasn't at the head of the ROB).
1017 // Save memory requests.
1018 savedReq = state->mainReq;
1019 savedSreqLow = state->sreqLow;
1020 savedSreqHigh = state->sreqHigh;
1023 WholeTranslationState *state =
1024 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1026 // Two translations when the request is split.
1027 DataTranslation<BaseDynInstPtr> *stransLow =
1028 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1029 DataTranslation<BaseDynInstPtr> *stransHigh =
1030 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1032 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1033 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1035 if (!translationCompleted()) {
1036 // The translation isn't yet complete, so we can't possibly have a
1037 // fault. Overwrite any existing fault we might have from a previous
1038 // execution of this instruction (e.g. an uncachable load that
1039 // couldn't execute because it wasn't at the head of the ROB).
1042 // Save memory requests.
1043 savedReq = state->mainReq;
1044 savedSreqLow = state->sreqLow;
1045 savedSreqHigh = state->sreqHigh;
1050 template<class Impl>
1052 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1054 fault = state->getFault();
1056 instFlags[IsStrictlyOrdered] = state->isStrictlyOrdered();
1058 if (fault == NoFault) {
1059 // save Paddr for a single req
1060 physEffAddrLow = state->getPaddr();
1062 // case for the request that has been split
1063 if (state->isSplit) {
1064 physEffAddrLow = state->sreqLow->getPaddr();
1065 physEffAddrHigh = state->sreqHigh->getPaddr();
1068 memReqFlags = state->getFlags();
1070 if (state->mainReq->isCondSwap()) {
1072 state->mainReq->setExtraData(*state->res);
1076 state->deleteReqs();
1080 translationCompleted(true);
1083 #endif // __CPU_BASE_DYN_INST_HH__