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45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
52 #include "arch/faults.hh"
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/full_system.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/system.hh"
71 * Defines a dynamic instruction context.
74 // Forward declaration.
78 class BaseDynInst : public FastAlloc, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
92 // The DynInstPtr type.
93 typedef typename Impl::DynInstPtr DynInstPtr;
94 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
96 // The list of instructions iterator type.
97 typedef typename std::list<DynInstPtr>::iterator ListIt;
100 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
101 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
104 /** The StaticInst used by this BaseDynInst. */
105 StaticInstPtr staticInst;
106 StaticInstPtr macroop;
108 ////////////////////////////////////////////
110 // INSTRUCTION EXECUTION
112 ////////////////////////////////////////////
113 /** InstRecord that tracks this instructions. */
114 Trace::InstRecord *traceData;
116 void demapPage(Addr vaddr, uint64_t asn)
118 cpu->demapPage(vaddr, asn);
120 void demapInstPage(Addr vaddr, uint64_t asn)
122 cpu->demapPage(vaddr, asn);
124 void demapDataPage(Addr vaddr, uint64_t asn)
126 cpu->demapPage(vaddr, asn);
129 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
131 Fault writeMem(uint8_t *data, unsigned size,
132 Addr addr, unsigned flags, uint64_t *res);
134 /** Splits a request in two if it crosses a dcache block. */
135 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
136 RequestPtr &sreqHigh);
138 /** Initiate a DTB address translation. */
139 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
140 RequestPtr sreqHigh, uint64_t *res,
143 /** Finish a DTB address translation. */
144 void finishTranslation(WholeTranslationState *state);
146 /** True if the DTB address translation has started. */
147 bool translationStarted;
149 /** True if the DTB address translation has completed. */
150 bool translationCompleted;
153 * Returns true if the DTB address translation is being delayed due to a hw
156 bool isTranslationDelayed() const
158 return (translationStarted && !translationCompleted);
162 * Saved memory requests (needed when the DTB address translation is
163 * delayed due to a hw page table walk).
166 RequestPtr savedSreqLow;
167 RequestPtr savedSreqHigh;
169 /** @todo: Consider making this private. */
171 /** The sequence number of the instruction. */
175 IqEntry, /// Instruction is in the IQ
176 RobEntry, /// Instruction is in the ROB
177 LsqEntry, /// Instruction is in the LSQ
178 Completed, /// Instruction has completed
179 ResultReady, /// Instruction has its result
180 CanIssue, /// Instruction can issue and execute
181 Issued, /// Instruction has issued
182 Executed, /// Instruction has executed
183 CanCommit, /// Instruction can commit
184 AtCommit, /// Instruction has reached commit
185 Committed, /// Instruction has committed
186 Squashed, /// Instruction is squashed
187 SquashedInIQ, /// Instruction is squashed in the IQ
188 SquashedInLSQ, /// Instruction is squashed in the LSQ
189 SquashedInROB, /// Instruction is squashed in the ROB
190 RecoverInst, /// Is a recover instruction
191 BlockingInst, /// Is a blocking instruction
192 ThreadsyncWait, /// Is a thread synchronization instruction
193 SerializeBefore, /// Needs to serialize on
194 /// instructions ahead of it
195 SerializeAfter, /// Needs to serialize instructions behind it
196 SerializeHandled, /// Serialization has been handled
200 /** The status of this BaseDynInst. Several bits can be set. */
201 std::bitset<NumStatus> status;
203 /** The thread this instruction is from. */
204 ThreadID threadNumber;
206 /** data address space ID, for loads & stores. */
209 /** How many source registers are ready. */
212 /** Pointer to the Impl's CPU object. */
215 /** Pointer to the thread state. */
218 /** The kind of fault this instruction has generated. */
221 /** Pointer to the data for the memory access. */
224 /** The effective virtual address (lds & stores only). */
227 /** The size of the request */
230 /** Is the effective virtual address valid. */
233 /** The effective physical address. */
236 /** The memory request flags (from translation). */
237 unsigned memReqFlags;
245 /** The result of the instruction; assumes for now that there's only one
246 * destination register.
250 /** Records changes to result? */
253 /** Did this instruction execute, or is it predicated false */
257 /** PC state for this instruction. */
260 /** Predicted PC state after this instruction. */
261 TheISA::PCState predPC;
263 /** If this is a branch that was predicted taken */
272 /** Whether or not the source register is ready.
273 * @todo: Not sure this should be here vs the derived class.
275 bool _readySrcRegIdx[MaxInstSrcRegs];
278 /** Flattened register index of the destination registers of this
281 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
283 /** Flattened register index of the source registers of this
286 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
288 /** Physical register index of the destination registers of this
291 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
293 /** Physical register index of the source registers of this
296 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
298 /** Physical register index of the previous producers of the
299 * architected destinations.
301 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
305 /** Returns the physical register index of the i'th destination
308 PhysRegIndex renamedDestRegIdx(int idx) const
310 return _destRegIdx[idx];
313 /** Returns the physical register index of the i'th source register. */
314 PhysRegIndex renamedSrcRegIdx(int idx) const
316 return _srcRegIdx[idx];
319 /** Returns the flattened register index of the i'th destination
322 TheISA::RegIndex flattenedDestRegIdx(int idx) const
324 return _flatDestRegIdx[idx];
327 /** Returns the flattened register index of the i'th source register */
328 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
330 return _flatSrcRegIdx[idx];
333 /** Returns the physical register index of the previous physical register
334 * that remapped to the same logical register index.
336 PhysRegIndex prevDestRegIdx(int idx) const
338 return _prevDestRegIdx[idx];
341 /** Renames a destination register to a physical register. Also records
342 * the previous physical register that the logical register mapped to.
344 void renameDestReg(int idx,
345 PhysRegIndex renamed_dest,
346 PhysRegIndex previous_rename)
348 _destRegIdx[idx] = renamed_dest;
349 _prevDestRegIdx[idx] = previous_rename;
352 /** Renames a source logical register to the physical register which
353 * has/will produce that logical register's result.
354 * @todo: add in whether or not the source register is ready.
356 void renameSrcReg(int idx, PhysRegIndex renamed_src)
358 _srcRegIdx[idx] = renamed_src;
361 /** Flattens a source architectural register index into a logical index.
363 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
365 _flatSrcRegIdx[idx] = flattened_src;
368 /** Flattens a destination architectural register index into a logical
371 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
373 _flatDestRegIdx[idx] = flattened_dest;
375 /** BaseDynInst constructor given a binary instruction.
376 * @param staticInst A StaticInstPtr to the underlying instruction.
377 * @param pc The PC state for the instruction.
378 * @param predPC The predicted next PC state for the instruction.
379 * @param seq_num The sequence number of the instruction.
380 * @param cpu Pointer to the instruction's CPU.
382 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
383 TheISA::PCState pc, TheISA::PCState predPC,
384 InstSeqNum seq_num, ImplCPU *cpu);
386 /** BaseDynInst constructor given a StaticInst pointer.
387 * @param _staticInst The StaticInst for this BaseDynInst.
389 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
391 /** BaseDynInst destructor. */
395 /** Function to initialize variables in the constructors. */
399 /** Dumps out contents of this BaseDynInst. */
402 /** Dumps out contents of this BaseDynInst into given string. */
403 void dump(std::string &outstring);
405 /** Read this CPU's ID. */
406 int cpuId() { return cpu->cpuId(); }
408 /** Read this context's system-wide ID **/
409 int contextId() { return thread->contextId(); }
411 /** Returns the fault type. */
412 Fault getFault() { return fault; }
414 /** Checks whether or not this instruction has had its branch target
415 * calculated yet. For now it is not utilized and is hacked to be
417 * @todo: Actually use this instruction.
419 bool doneTargCalc() { return false; }
421 /** Set the predicted target of this current instruction. */
422 void setPredTarg(const TheISA::PCState &_predPC)
427 const TheISA::PCState &readPredTarg() { return predPC; }
429 /** Returns the predicted PC immediately after the branch. */
430 Addr predInstAddr() { return predPC.instAddr(); }
432 /** Returns the predicted PC two instructions after the branch */
433 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
435 /** Returns the predicted micro PC after the branch */
436 Addr predMicroPC() { return predPC.microPC(); }
438 /** Returns whether the instruction was predicted taken or not. */
444 void setPredTaken(bool predicted_taken)
446 predTaken = predicted_taken;
449 /** Returns whether the instruction mispredicted. */
452 TheISA::PCState tempPC = pc;
453 TheISA::advancePC(tempPC, staticInst);
454 return !(tempPC == predPC);
458 // Instruction types. Forward checks to StaticInst object.
460 bool isNop() const { return staticInst->isNop(); }
461 bool isMemRef() const { return staticInst->isMemRef(); }
462 bool isLoad() const { return staticInst->isLoad(); }
463 bool isStore() const { return staticInst->isStore(); }
464 bool isStoreConditional() const
465 { return staticInst->isStoreConditional(); }
466 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
467 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
468 bool isInteger() const { return staticInst->isInteger(); }
469 bool isFloating() const { return staticInst->isFloating(); }
470 bool isControl() const { return staticInst->isControl(); }
471 bool isCall() const { return staticInst->isCall(); }
472 bool isReturn() const { return staticInst->isReturn(); }
473 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
474 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
475 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
476 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
477 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
478 bool isThreadSync() const { return staticInst->isThreadSync(); }
479 bool isSerializing() const { return staticInst->isSerializing(); }
480 bool isSerializeBefore() const
481 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
482 bool isSerializeAfter() const
483 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
484 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
485 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
486 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
487 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
488 bool isQuiesce() const { return staticInst->isQuiesce(); }
489 bool isIprAccess() const { return staticInst->isIprAccess(); }
490 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
491 bool isSyscall() const { return staticInst->isSyscall(); }
492 bool isMacroop() const { return staticInst->isMacroop(); }
493 bool isMicroop() const { return staticInst->isMicroop(); }
494 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
495 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
496 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
497 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
499 /** Temporarily sets this instruction as a serialize before instruction. */
500 void setSerializeBefore() { status.set(SerializeBefore); }
502 /** Clears the serializeBefore part of this instruction. */
503 void clearSerializeBefore() { status.reset(SerializeBefore); }
505 /** Checks if this serializeBefore is only temporarily set. */
506 bool isTempSerializeBefore() { return status[SerializeBefore]; }
508 /** Temporarily sets this instruction as a serialize after instruction. */
509 void setSerializeAfter() { status.set(SerializeAfter); }
511 /** Clears the serializeAfter part of this instruction.*/
512 void clearSerializeAfter() { status.reset(SerializeAfter); }
514 /** Checks if this serializeAfter is only temporarily set. */
515 bool isTempSerializeAfter() { return status[SerializeAfter]; }
517 /** Sets the serialization part of this instruction as handled. */
518 void setSerializeHandled() { status.set(SerializeHandled); }
520 /** Checks if the serialization part of this instruction has been
521 * handled. This does not apply to the temporary serializing
522 * state; it only applies to this instruction's own permanent
525 bool isSerializeHandled() { return status[SerializeHandled]; }
527 /** Returns the opclass of this instruction. */
528 OpClass opClass() const { return staticInst->opClass(); }
530 /** Returns the branch target address. */
531 TheISA::PCState branchTarget() const
532 { return staticInst->branchTarget(pc); }
534 /** Returns the number of source registers. */
535 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
537 /** Returns the number of destination registers. */
538 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
540 // the following are used to track physical register usage
541 // for machines with separate int & FP reg files
542 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
543 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
545 /** Returns the logical register index of the i'th destination register. */
546 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
548 /** Returns the logical register index of the i'th source register. */
549 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
551 /** Returns the result of an integer instruction. */
552 uint64_t readIntResult() { return instResult.integer; }
554 /** Returns the result of a floating point instruction. */
555 float readFloatResult() { return (float)instResult.dbl; }
557 /** Returns the result of a floating point (double) instruction. */
558 double readDoubleResult() { return instResult.dbl; }
560 /** Records an integer register being set to a value. */
561 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
564 instResult.integer = val;
567 /** Records an fp register being set to a value. */
568 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
573 instResult.dbl = (double)val;
574 else if (width == 64)
575 instResult.dbl = val;
577 panic("Unsupported width!");
581 /** Records an fp register being set to a value. */
582 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
585 instResult.dbl = (double)val;
588 /** Records an fp register being set to an integer value. */
589 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
593 instResult.integer = val;
596 /** Records an fp register being set to an integer value. */
597 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
600 instResult.integer = val;
603 /** Records that one of the source registers is ready. */
604 void markSrcRegReady();
606 /** Marks a specific register as ready. */
607 void markSrcRegReady(RegIndex src_idx);
609 /** Returns if a source register is ready. */
610 bool isReadySrcRegIdx(int idx) const
612 return this->_readySrcRegIdx[idx];
615 /** Sets this instruction as completed. */
616 void setCompleted() { status.set(Completed); }
618 /** Returns whether or not this instruction is completed. */
619 bool isCompleted() const { return status[Completed]; }
621 /** Marks the result as ready. */
622 void setResultReady() { status.set(ResultReady); }
624 /** Returns whether or not the result is ready. */
625 bool isResultReady() const { return status[ResultReady]; }
627 /** Sets this instruction as ready to issue. */
628 void setCanIssue() { status.set(CanIssue); }
630 /** Returns whether or not this instruction is ready to issue. */
631 bool readyToIssue() const { return status[CanIssue]; }
633 /** Clears this instruction being able to issue. */
634 void clearCanIssue() { status.reset(CanIssue); }
636 /** Sets this instruction as issued from the IQ. */
637 void setIssued() { status.set(Issued); }
639 /** Returns whether or not this instruction has issued. */
640 bool isIssued() const { return status[Issued]; }
642 /** Clears this instruction as being issued. */
643 void clearIssued() { status.reset(Issued); }
645 /** Sets this instruction as executed. */
646 void setExecuted() { status.set(Executed); }
648 /** Returns whether or not this instruction has executed. */
649 bool isExecuted() const { return status[Executed]; }
651 /** Sets this instruction as ready to commit. */
652 void setCanCommit() { status.set(CanCommit); }
654 /** Clears this instruction as being ready to commit. */
655 void clearCanCommit() { status.reset(CanCommit); }
657 /** Returns whether or not this instruction is ready to commit. */
658 bool readyToCommit() const { return status[CanCommit]; }
660 void setAtCommit() { status.set(AtCommit); }
662 bool isAtCommit() { return status[AtCommit]; }
664 /** Sets this instruction as committed. */
665 void setCommitted() { status.set(Committed); }
667 /** Returns whether or not this instruction is committed. */
668 bool isCommitted() const { return status[Committed]; }
670 /** Sets this instruction as squashed. */
671 void setSquashed() { status.set(Squashed); }
673 /** Returns whether or not this instruction is squashed. */
674 bool isSquashed() const { return status[Squashed]; }
676 //Instruction Queue Entry
677 //-----------------------
678 /** Sets this instruction as a entry the IQ. */
679 void setInIQ() { status.set(IqEntry); }
681 /** Sets this instruction as a entry the IQ. */
682 void clearInIQ() { status.reset(IqEntry); }
684 /** Returns whether or not this instruction has issued. */
685 bool isInIQ() const { return status[IqEntry]; }
687 /** Sets this instruction as squashed in the IQ. */
688 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
690 /** Returns whether or not this instruction is squashed in the IQ. */
691 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
694 //Load / Store Queue Functions
695 //-----------------------
696 /** Sets this instruction as a entry the LSQ. */
697 void setInLSQ() { status.set(LsqEntry); }
699 /** Sets this instruction as a entry the LSQ. */
700 void removeInLSQ() { status.reset(LsqEntry); }
702 /** Returns whether or not this instruction is in the LSQ. */
703 bool isInLSQ() const { return status[LsqEntry]; }
705 /** Sets this instruction as squashed in the LSQ. */
706 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
708 /** Returns whether or not this instruction is squashed in the LSQ. */
709 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
712 //Reorder Buffer Functions
713 //-----------------------
714 /** Sets this instruction as a entry the ROB. */
715 void setInROB() { status.set(RobEntry); }
717 /** Sets this instruction as a entry the ROB. */
718 void clearInROB() { status.reset(RobEntry); }
720 /** Returns whether or not this instruction is in the ROB. */
721 bool isInROB() const { return status[RobEntry]; }
723 /** Sets this instruction as squashed in the ROB. */
724 void setSquashedInROB() { status.set(SquashedInROB); }
726 /** Returns whether or not this instruction is squashed in the ROB. */
727 bool isSquashedInROB() const { return status[SquashedInROB]; }
729 /** Read the PC state of this instruction. */
730 const TheISA::PCState pcState() const { return pc; }
732 /** Set the PC state of this instruction. */
733 const void pcState(const TheISA::PCState &val) { pc = val; }
735 /** Read the PC of this instruction. */
736 const Addr instAddr() const { return pc.instAddr(); }
738 /** Read the PC of the next instruction. */
739 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
741 /**Read the micro PC of this instruction. */
742 const Addr microPC() const { return pc.microPC(); }
749 void setPredicate(bool val)
754 traceData->setPredicate(val);
758 /** Sets the ASID. */
759 void setASID(short addr_space_id) { asid = addr_space_id; }
761 /** Sets the thread id. */
762 void setTid(ThreadID tid) { threadNumber = tid; }
764 /** Sets the pointer to the thread state. */
765 void setThreadState(ImplState *state) { thread = state; }
767 /** Returns the thread context. */
768 ThreadContext *tcBase() { return thread->getTC(); }
771 /** Instruction effective address.
772 * @todo: Consider if this is necessary or not.
776 /** Whether or not the effective address calculation is completed.
777 * @todo: Consider if this is necessary or not.
781 /** Is this instruction's memory access uncacheable. */
784 /** Has this instruction generated a memory request. */
788 /** Sets the effective address. */
789 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
791 /** Returns the effective address. */
792 const Addr &getEA() const { return instEffAddr; }
794 /** Returns whether or not the eff. addr. calculation has been completed. */
795 bool doneEACalc() { return eaCalcDone; }
797 /** Returns whether or not the eff. addr. source registers are ready. */
800 /** Whether or not the memory operation is done. */
803 /** Is this instruction's memory access uncacheable. */
804 bool uncacheable() { return isUncacheable; }
806 /** Has this instruction generated a memory request. */
807 bool hasRequest() { return reqMade; }
810 /** Load queue index. */
813 /** Store queue index. */
816 /** Iterator pointing to this BaseDynInst in the list of all insts. */
819 /** Returns iterator to this instruction in the list of all insts. */
820 ListIt &getInstListIt() { return instListIt; }
822 /** Sets iterator for this instruction in the list of all insts. */
823 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
826 /** Returns the number of consecutive store conditional failures. */
827 unsigned readStCondFailures()
828 { return thread->storeCondFailures; }
830 /** Sets the number of consecutive store conditional failures. */
831 void setStCondFailures(unsigned sc_failures)
832 { thread->storeCondFailures = sc_failures; }
837 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
838 unsigned size, unsigned flags)
842 Request *sreqLow = NULL;
843 Request *sreqHigh = NULL;
845 if (reqMade && translationStarted) {
847 sreqLow = savedSreqLow;
848 sreqHigh = savedSreqHigh;
850 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
851 thread->contextId(), threadNumber);
853 // Only split the request if the ISA supports unaligned accesses.
854 if (TheISA::HasUnalignedMemAcc) {
855 splitRequest(req, sreqLow, sreqHigh);
857 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
860 if (translationCompleted) {
861 if (fault == NoFault) {
862 effAddr = req->getVaddr();
865 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
867 // Commit will have to clean up whatever happened. Set this
868 // instruction as executed.
872 if (fault != NoFault) {
873 // Return a fixed value to keep simulation deterministic even
874 // along misspeculated paths.
881 traceData->setAddr(addr);
889 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
890 Addr addr, unsigned flags, uint64_t *res)
893 traceData->setAddr(addr);
898 Request *sreqLow = NULL;
899 Request *sreqHigh = NULL;
901 if (reqMade && translationStarted) {
903 sreqLow = savedSreqLow;
904 sreqHigh = savedSreqHigh;
906 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
907 thread->contextId(), threadNumber);
909 // Only split the request if the ISA supports unaligned accesses.
910 if (TheISA::HasUnalignedMemAcc) {
911 splitRequest(req, sreqLow, sreqHigh);
913 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
916 if (fault == NoFault && translationCompleted) {
917 effAddr = req->getVaddr();
920 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
928 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
929 RequestPtr &sreqHigh)
931 // Check to see if the request crosses the next level block boundary.
932 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
933 Addr addr = req->getVaddr();
934 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
935 assert(split_addr <= addr || split_addr - addr < block_size);
938 if (split_addr > addr) {
939 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
945 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
946 RequestPtr sreqHigh, uint64_t *res,
949 translationStarted = true;
951 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
952 WholeTranslationState *state =
953 new WholeTranslationState(req, NULL, res, mode);
955 // One translation if the request isn't split.
956 DataTranslation<BaseDynInstPtr> *trans =
957 new DataTranslation<BaseDynInstPtr>(this, state);
958 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
959 if (!translationCompleted) {
960 // Save memory requests.
961 savedReq = state->mainReq;
962 savedSreqLow = state->sreqLow;
963 savedSreqHigh = state->sreqHigh;
966 WholeTranslationState *state =
967 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
969 // Two translations when the request is split.
970 DataTranslation<BaseDynInstPtr> *stransLow =
971 new DataTranslation<BaseDynInstPtr>(this, state, 0);
972 DataTranslation<BaseDynInstPtr> *stransHigh =
973 new DataTranslation<BaseDynInstPtr>(this, state, 1);
975 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
976 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
977 if (!translationCompleted) {
978 // Save memory requests.
979 savedReq = state->mainReq;
980 savedSreqLow = state->sreqLow;
981 savedSreqHigh = state->sreqHigh;
988 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
990 fault = state->getFault();
992 if (state->isUncacheable())
993 isUncacheable = true;
995 if (fault == NoFault) {
996 physEffAddr = state->getPaddr();
997 memReqFlags = state->getFlags();
999 if (state->mainReq->isCondSwap()) {
1001 state->mainReq->setExtraData(*state->res);
1005 state->deleteReqs();
1009 translationCompleted = true;
1012 #endif // __CPU_BASE_DYN_INST_HH__