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46 #ifndef __CPU_BASE_DYN_INST_HH__
47 #define __CPU_BASE_DYN_INST_HH__
54 #include "arch/utility.hh"
55 #include "base/trace.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/checker/cpu.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exec_context.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/inst_seq.hh"
62 #include "cpu/op_class.hh"
63 #include "cpu/static_inst.hh"
64 #include "cpu/translation.hh"
65 #include "mem/packet.hh"
66 #include "sim/byteswap.hh"
67 #include "sim/fault_fwd.hh"
68 #include "sim/system.hh"
73 * Defines a dynamic instruction context.
77 class BaseDynInst : public ExecContext, public RefCounted
80 // Typedef for the CPU.
81 typedef typename Impl::CPUType ImplCPU;
82 typedef typename ImplCPU::ImplState ImplState;
84 // Logical register index type.
85 typedef TheISA::RegIndex RegIndex;
87 // The DynInstPtr type.
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
91 // The list of instructions iterator type.
92 typedef typename std::list<DynInstPtr>::iterator ListIt;
95 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
96 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
102 void set(uint64_t i) { integer = i; }
103 void set(double d) { dbl = d; }
104 void get(uint64_t& i) { i = integer; }
105 void get(double& d) { d = dbl; }
110 IqEntry, /// Instruction is in the IQ
111 RobEntry, /// Instruction is in the ROB
112 LsqEntry, /// Instruction is in the LSQ
113 Completed, /// Instruction has completed
114 ResultReady, /// Instruction has its result
115 CanIssue, /// Instruction can issue and execute
116 Issued, /// Instruction has issued
117 Executed, /// Instruction has executed
118 CanCommit, /// Instruction can commit
119 AtCommit, /// Instruction has reached commit
120 Committed, /// Instruction has committed
121 Squashed, /// Instruction is squashed
122 SquashedInIQ, /// Instruction is squashed in the IQ
123 SquashedInLSQ, /// Instruction is squashed in the LSQ
124 SquashedInROB, /// Instruction is squashed in the ROB
125 RecoverInst, /// Is a recover instruction
126 BlockingInst, /// Is a blocking instruction
127 ThreadsyncWait, /// Is a thread synchronization instruction
128 SerializeBefore, /// Needs to serialize on
129 /// instructions ahead of it
130 SerializeAfter, /// Needs to serialize instructions behind it
131 SerializeHandled, /// Serialization has been handled
137 TranslationCompleted,
138 PossibleLoadViolation,
144 /** Whether or not the effective address calculation is completed.
145 * @todo: Consider if this is necessary or not.
155 /** The sequence number of the instruction. */
158 /** The StaticInst used by this BaseDynInst. */
159 const StaticInstPtr staticInst;
161 /** Pointer to the Impl's CPU object. */
164 BaseCPU *getCpuPtr() { return cpu; }
166 /** Pointer to the thread state. */
169 /** The kind of fault this instruction has generated. */
172 /** InstRecord that tracks this instructions. */
173 Trace::InstRecord *traceData;
176 /** The result of the instruction; assumes an instruction can have many
177 * destination registers.
179 std::queue<Result> instResult;
181 /** PC state for this instruction. */
184 /* An amalgamation of a lot of boolean values into one */
185 std::bitset<MaxFlags> instFlags;
187 /** The status of this BaseDynInst. Several bits can be set. */
188 std::bitset<NumStatus> status;
190 /** Whether or not the source register is ready.
191 * @todo: Not sure this should be here vs the derived class.
193 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
196 /** The thread this instruction is from. */
197 ThreadID threadNumber;
199 /** Iterator pointing to this BaseDynInst in the list of all insts. */
202 ////////////////////// Branch Data ///////////////
203 /** Predicted PC state after this instruction. */
204 TheISA::PCState predPC;
206 /** The Macroop if one exists */
207 const StaticInstPtr macroop;
209 /** How many source registers are ready. */
213 /////////////////////// Load Store Data //////////////////////
214 /** The effective virtual address (lds & stores only). */
217 /** The effective physical address. */
220 /** The memory request flags (from translation). */
221 unsigned memReqFlags;
223 /** data address space ID, for loads & stores. */
226 /** The size of the request */
229 /** Pointer to the data for the memory access. */
232 /** Load queue index. */
235 /** Store queue index. */
239 /////////////////////// TLB Miss //////////////////////
241 * Saved memory requests (needed when the DTB address translation is
242 * delayed due to a hw page table walk).
245 RequestPtr savedSreqLow;
246 RequestPtr savedSreqHigh;
248 /////////////////////// Checker //////////////////////
249 // Need a copy of main request pointer to verify on writes.
250 RequestPtr reqToVerify;
253 /** Instruction effective address.
254 * @todo: Consider if this is necessary or not.
259 /** Flattened register index of the destination registers of this
262 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
264 /** Physical register index of the destination registers of this
267 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
269 /** Physical register index of the source registers of this
272 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
274 /** Physical register index of the previous producers of the
275 * architected destinations.
277 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
281 /** Records changes to result? */
282 void recordResult(bool f) { instFlags[RecordResult] = f; }
284 /** Is the effective virtual address valid. */
285 bool effAddrValid() const { return instFlags[EffAddrValid]; }
287 /** Whether or not the memory operation is done. */
288 bool memOpDone() const { return instFlags[MemOpDone]; }
289 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
292 ////////////////////////////////////////////
294 // INSTRUCTION EXECUTION
296 ////////////////////////////////////////////
298 void demapPage(Addr vaddr, uint64_t asn)
300 cpu->demapPage(vaddr, asn);
302 void demapInstPage(Addr vaddr, uint64_t asn)
304 cpu->demapPage(vaddr, asn);
306 void demapDataPage(Addr vaddr, uint64_t asn)
308 cpu->demapPage(vaddr, asn);
311 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
313 Fault writeMem(uint8_t *data, unsigned size,
314 Addr addr, unsigned flags, uint64_t *res);
316 /** Splits a request in two if it crosses a dcache block. */
317 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
318 RequestPtr &sreqHigh);
320 /** Initiate a DTB address translation. */
321 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
322 RequestPtr sreqHigh, uint64_t *res,
325 /** Finish a DTB address translation. */
326 void finishTranslation(WholeTranslationState *state);
328 /** True if the DTB address translation has started. */
329 bool translationStarted() const { return instFlags[TranslationStarted]; }
330 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
332 /** True if the DTB address translation has completed. */
333 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
334 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
336 /** True if this address was found to match a previous load and they issued
337 * out of order. If that happend, then it's only a problem if an incoming
338 * snoop invalidate modifies the line, in which case we need to squash.
339 * If nothing modified the line the order doesn't matter.
341 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
342 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
344 /** True if the address hit a external snoop while sitting in the LSQ.
345 * If this is true and a older instruction sees it, this instruction must
348 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
349 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
352 * Returns true if the DTB address translation is being delayed due to a hw
355 bool isTranslationDelayed() const
357 return (translationStarted() && !translationCompleted());
365 /** Returns the physical register index of the i'th destination
368 PhysRegIndex renamedDestRegIdx(int idx) const
370 return _destRegIdx[idx];
373 /** Returns the physical register index of the i'th source register. */
374 PhysRegIndex renamedSrcRegIdx(int idx) const
376 assert(TheISA::MaxInstSrcRegs > idx);
377 return _srcRegIdx[idx];
380 /** Returns the flattened register index of the i'th destination
383 TheISA::RegIndex flattenedDestRegIdx(int idx) const
385 return _flatDestRegIdx[idx];
388 /** Returns the physical register index of the previous physical register
389 * that remapped to the same logical register index.
391 PhysRegIndex prevDestRegIdx(int idx) const
393 return _prevDestRegIdx[idx];
396 /** Renames a destination register to a physical register. Also records
397 * the previous physical register that the logical register mapped to.
399 void renameDestReg(int idx,
400 PhysRegIndex renamed_dest,
401 PhysRegIndex previous_rename)
403 _destRegIdx[idx] = renamed_dest;
404 _prevDestRegIdx[idx] = previous_rename;
407 /** Renames a source logical register to the physical register which
408 * has/will produce that logical register's result.
409 * @todo: add in whether or not the source register is ready.
411 void renameSrcReg(int idx, PhysRegIndex renamed_src)
413 _srcRegIdx[idx] = renamed_src;
416 /** Flattens a destination architectural register index into a logical
419 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
421 _flatDestRegIdx[idx] = flattened_dest;
423 /** BaseDynInst constructor given a binary instruction.
424 * @param staticInst A StaticInstPtr to the underlying instruction.
425 * @param pc The PC state for the instruction.
426 * @param predPC The predicted next PC state for the instruction.
427 * @param seq_num The sequence number of the instruction.
428 * @param cpu Pointer to the instruction's CPU.
430 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
431 TheISA::PCState pc, TheISA::PCState predPC,
432 InstSeqNum seq_num, ImplCPU *cpu);
434 /** BaseDynInst constructor given a StaticInst pointer.
435 * @param _staticInst The StaticInst for this BaseDynInst.
437 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
439 /** BaseDynInst destructor. */
443 /** Function to initialize variables in the constructors. */
447 /** Dumps out contents of this BaseDynInst. */
450 /** Dumps out contents of this BaseDynInst into given string. */
451 void dump(std::string &outstring);
453 /** Read this CPU's ID. */
454 int cpuId() const { return cpu->cpuId(); }
456 /** Read this CPU's Socket ID. */
457 uint32_t socketId() const { return cpu->socketId(); }
459 /** Read this CPU's data requestor ID */
460 MasterID masterId() const { return cpu->dataMasterId(); }
462 /** Read this context's system-wide ID **/
463 int contextId() const { return thread->contextId(); }
465 /** Returns the fault type. */
466 Fault getFault() const { return fault; }
468 /** Checks whether or not this instruction has had its branch target
469 * calculated yet. For now it is not utilized and is hacked to be
471 * @todo: Actually use this instruction.
473 bool doneTargCalc() { return false; }
475 /** Set the predicted target of this current instruction. */
476 void setPredTarg(const TheISA::PCState &_predPC)
481 const TheISA::PCState &readPredTarg() { return predPC; }
483 /** Returns the predicted PC immediately after the branch. */
484 Addr predInstAddr() { return predPC.instAddr(); }
486 /** Returns the predicted PC two instructions after the branch */
487 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
489 /** Returns the predicted micro PC after the branch */
490 Addr predMicroPC() { return predPC.microPC(); }
492 /** Returns whether the instruction was predicted taken or not. */
495 return instFlags[PredTaken];
498 void setPredTaken(bool predicted_taken)
500 instFlags[PredTaken] = predicted_taken;
503 /** Returns whether the instruction mispredicted. */
506 TheISA::PCState tempPC = pc;
507 TheISA::advancePC(tempPC, staticInst);
508 return !(tempPC == predPC);
512 // Instruction types. Forward checks to StaticInst object.
514 bool isNop() const { return staticInst->isNop(); }
515 bool isMemRef() const { return staticInst->isMemRef(); }
516 bool isLoad() const { return staticInst->isLoad(); }
517 bool isStore() const { return staticInst->isStore(); }
518 bool isStoreConditional() const
519 { return staticInst->isStoreConditional(); }
520 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
521 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
522 bool isInteger() const { return staticInst->isInteger(); }
523 bool isFloating() const { return staticInst->isFloating(); }
524 bool isControl() const { return staticInst->isControl(); }
525 bool isCall() const { return staticInst->isCall(); }
526 bool isReturn() const { return staticInst->isReturn(); }
527 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
528 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
529 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
530 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
531 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
532 bool isThreadSync() const { return staticInst->isThreadSync(); }
533 bool isSerializing() const { return staticInst->isSerializing(); }
534 bool isSerializeBefore() const
535 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
536 bool isSerializeAfter() const
537 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
538 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
539 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
540 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
541 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
542 bool isQuiesce() const { return staticInst->isQuiesce(); }
543 bool isIprAccess() const { return staticInst->isIprAccess(); }
544 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
545 bool isSyscall() const { return staticInst->isSyscall(); }
546 bool isMacroop() const { return staticInst->isMacroop(); }
547 bool isMicroop() const { return staticInst->isMicroop(); }
548 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
549 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
550 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
551 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
553 /** Temporarily sets this instruction as a serialize before instruction. */
554 void setSerializeBefore() { status.set(SerializeBefore); }
556 /** Clears the serializeBefore part of this instruction. */
557 void clearSerializeBefore() { status.reset(SerializeBefore); }
559 /** Checks if this serializeBefore is only temporarily set. */
560 bool isTempSerializeBefore() { return status[SerializeBefore]; }
562 /** Temporarily sets this instruction as a serialize after instruction. */
563 void setSerializeAfter() { status.set(SerializeAfter); }
565 /** Clears the serializeAfter part of this instruction.*/
566 void clearSerializeAfter() { status.reset(SerializeAfter); }
568 /** Checks if this serializeAfter is only temporarily set. */
569 bool isTempSerializeAfter() { return status[SerializeAfter]; }
571 /** Sets the serialization part of this instruction as handled. */
572 void setSerializeHandled() { status.set(SerializeHandled); }
574 /** Checks if the serialization part of this instruction has been
575 * handled. This does not apply to the temporary serializing
576 * state; it only applies to this instruction's own permanent
579 bool isSerializeHandled() { return status[SerializeHandled]; }
581 /** Returns the opclass of this instruction. */
582 OpClass opClass() const { return staticInst->opClass(); }
584 /** Returns the branch target address. */
585 TheISA::PCState branchTarget() const
586 { return staticInst->branchTarget(pc); }
588 /** Returns the number of source registers. */
589 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
591 /** Returns the number of destination registers. */
592 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
594 // the following are used to track physical register usage
595 // for machines with separate int & FP reg files
596 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
597 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
599 /** Returns the logical register index of the i'th destination register. */
600 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
602 /** Returns the logical register index of the i'th source register. */
603 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
605 /** Pops a result off the instResult queue */
609 if (!instResult.empty()) {
610 instResult.front().get(t);
615 /** Read the most recent result stored by this instruction */
617 void readResult(T& t)
619 instResult.back().get(t);
622 /** Pushes a result onto the instResult queue */
626 if (instFlags[RecordResult]) {
629 instResult.push(instRes);
633 /** Records an integer register being set to a value. */
634 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
636 setResult<uint64_t>(val);
639 /** Records a CC register being set to a value. */
640 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
642 setResult<uint64_t>(val);
645 /** Records an fp register being set to a value. */
646 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
648 setResult<double>(val);
651 /** Records an fp register being set to an integer value. */
652 void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val)
654 setResult<uint64_t>(val);
657 /** Records that one of the source registers is ready. */
658 void markSrcRegReady();
660 /** Marks a specific register as ready. */
661 void markSrcRegReady(RegIndex src_idx);
663 /** Returns if a source register is ready. */
664 bool isReadySrcRegIdx(int idx) const
666 return this->_readySrcRegIdx[idx];
669 /** Sets this instruction as completed. */
670 void setCompleted() { status.set(Completed); }
672 /** Returns whether or not this instruction is completed. */
673 bool isCompleted() const { return status[Completed]; }
675 /** Marks the result as ready. */
676 void setResultReady() { status.set(ResultReady); }
678 /** Returns whether or not the result is ready. */
679 bool isResultReady() const { return status[ResultReady]; }
681 /** Sets this instruction as ready to issue. */
682 void setCanIssue() { status.set(CanIssue); }
684 /** Returns whether or not this instruction is ready to issue. */
685 bool readyToIssue() const { return status[CanIssue]; }
687 /** Clears this instruction being able to issue. */
688 void clearCanIssue() { status.reset(CanIssue); }
690 /** Sets this instruction as issued from the IQ. */
691 void setIssued() { status.set(Issued); }
693 /** Returns whether or not this instruction has issued. */
694 bool isIssued() const { return status[Issued]; }
696 /** Clears this instruction as being issued. */
697 void clearIssued() { status.reset(Issued); }
699 /** Sets this instruction as executed. */
700 void setExecuted() { status.set(Executed); }
702 /** Returns whether or not this instruction has executed. */
703 bool isExecuted() const { return status[Executed]; }
705 /** Sets this instruction as ready to commit. */
706 void setCanCommit() { status.set(CanCommit); }
708 /** Clears this instruction as being ready to commit. */
709 void clearCanCommit() { status.reset(CanCommit); }
711 /** Returns whether or not this instruction is ready to commit. */
712 bool readyToCommit() const { return status[CanCommit]; }
714 void setAtCommit() { status.set(AtCommit); }
716 bool isAtCommit() { return status[AtCommit]; }
718 /** Sets this instruction as committed. */
719 void setCommitted() { status.set(Committed); }
721 /** Returns whether or not this instruction is committed. */
722 bool isCommitted() const { return status[Committed]; }
724 /** Sets this instruction as squashed. */
725 void setSquashed() { status.set(Squashed); }
727 /** Returns whether or not this instruction is squashed. */
728 bool isSquashed() const { return status[Squashed]; }
730 //Instruction Queue Entry
731 //-----------------------
732 /** Sets this instruction as a entry the IQ. */
733 void setInIQ() { status.set(IqEntry); }
735 /** Sets this instruction as a entry the IQ. */
736 void clearInIQ() { status.reset(IqEntry); }
738 /** Returns whether or not this instruction has issued. */
739 bool isInIQ() const { return status[IqEntry]; }
741 /** Sets this instruction as squashed in the IQ. */
742 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
744 /** Returns whether or not this instruction is squashed in the IQ. */
745 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
748 //Load / Store Queue Functions
749 //-----------------------
750 /** Sets this instruction as a entry the LSQ. */
751 void setInLSQ() { status.set(LsqEntry); }
753 /** Sets this instruction as a entry the LSQ. */
754 void removeInLSQ() { status.reset(LsqEntry); }
756 /** Returns whether or not this instruction is in the LSQ. */
757 bool isInLSQ() const { return status[LsqEntry]; }
759 /** Sets this instruction as squashed in the LSQ. */
760 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
762 /** Returns whether or not this instruction is squashed in the LSQ. */
763 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
766 //Reorder Buffer Functions
767 //-----------------------
768 /** Sets this instruction as a entry the ROB. */
769 void setInROB() { status.set(RobEntry); }
771 /** Sets this instruction as a entry the ROB. */
772 void clearInROB() { status.reset(RobEntry); }
774 /** Returns whether or not this instruction is in the ROB. */
775 bool isInROB() const { return status[RobEntry]; }
777 /** Sets this instruction as squashed in the ROB. */
778 void setSquashedInROB() { status.set(SquashedInROB); }
780 /** Returns whether or not this instruction is squashed in the ROB. */
781 bool isSquashedInROB() const { return status[SquashedInROB]; }
783 /** Read the PC state of this instruction. */
784 TheISA::PCState pcState() const { return pc; }
786 /** Set the PC state of this instruction. */
787 void pcState(const TheISA::PCState &val) { pc = val; }
789 /** Read the PC of this instruction. */
790 const Addr instAddr() const { return pc.instAddr(); }
792 /** Read the PC of the next instruction. */
793 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
795 /**Read the micro PC of this instruction. */
796 const Addr microPC() const { return pc.microPC(); }
800 return instFlags[Predicate];
803 void setPredicate(bool val)
805 instFlags[Predicate] = val;
808 traceData->setPredicate(val);
812 /** Sets the ASID. */
813 void setASID(short addr_space_id) { asid = addr_space_id; }
815 /** Sets the thread id. */
816 void setTid(ThreadID tid) { threadNumber = tid; }
818 /** Sets the pointer to the thread state. */
819 void setThreadState(ImplState *state) { thread = state; }
821 /** Returns the thread context. */
822 ThreadContext *tcBase() { return thread->getTC(); }
825 /** Sets the effective address. */
826 void setEA(Addr ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
828 /** Returns the effective address. */
829 Addr getEA() const { return instEffAddr; }
831 /** Returns whether or not the eff. addr. calculation has been completed. */
832 bool doneEACalc() { return instFlags[EACalcDone]; }
834 /** Returns whether or not the eff. addr. source registers are ready. */
837 /** Is this instruction's memory access uncacheable. */
838 bool uncacheable() { return instFlags[IsUncacheable]; }
840 /** Has this instruction generated a memory request. */
841 bool hasRequest() { return instFlags[ReqMade]; }
843 /** Returns iterator to this instruction in the list of all insts. */
844 ListIt &getInstListIt() { return instListIt; }
846 /** Sets iterator for this instruction in the list of all insts. */
847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
850 /** Returns the number of consecutive store conditional failures. */
851 unsigned int readStCondFailures() const
852 { return thread->storeCondFailures; }
854 /** Sets the number of consecutive store conditional failures. */
855 void setStCondFailures(unsigned int sc_failures)
856 { thread->storeCondFailures = sc_failures; }
861 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
862 unsigned size, unsigned flags)
864 instFlags[ReqMade] = true;
866 Request *sreqLow = NULL;
867 Request *sreqHigh = NULL;
869 if (instFlags[ReqMade] && translationStarted()) {
871 sreqLow = savedSreqLow;
872 sreqHigh = savedSreqHigh;
874 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
875 thread->contextId(), threadNumber);
877 req->taskId(cpu->taskId());
879 // Only split the request if the ISA supports unaligned accesses.
880 if (TheISA::HasUnalignedMemAcc) {
881 splitRequest(req, sreqLow, sreqHigh);
883 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
886 if (translationCompleted()) {
887 if (fault == NoFault) {
888 effAddr = req->getVaddr();
890 instFlags[EffAddrValid] = true;
893 if (reqToVerify != NULL) {
896 reqToVerify = new Request(*req);
898 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
900 // Commit will have to clean up whatever happened. Set this
901 // instruction as executed.
905 if (fault != NoFault) {
906 // Return a fixed value to keep simulation deterministic even
907 // along misspeculated paths.
914 traceData->setAddr(addr);
922 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
923 Addr addr, unsigned flags, uint64_t *res)
926 traceData->setAddr(addr);
929 instFlags[ReqMade] = true;
931 Request *sreqLow = NULL;
932 Request *sreqHigh = NULL;
934 if (instFlags[ReqMade] && translationStarted()) {
936 sreqLow = savedSreqLow;
937 sreqHigh = savedSreqHigh;
939 req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
940 thread->contextId(), threadNumber);
942 req->taskId(cpu->taskId());
944 // Only split the request if the ISA supports unaligned accesses.
945 if (TheISA::HasUnalignedMemAcc) {
946 splitRequest(req, sreqLow, sreqHigh);
948 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
951 if (fault == NoFault && translationCompleted()) {
952 effAddr = req->getVaddr();
954 instFlags[EffAddrValid] = true;
957 if (reqToVerify != NULL) {
960 reqToVerify = new Request(*req);
962 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
970 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
971 RequestPtr &sreqHigh)
973 // Check to see if the request crosses the next level block boundary.
974 unsigned block_size = cpu->cacheLineSize();
975 Addr addr = req->getVaddr();
976 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
977 assert(split_addr <= addr || split_addr - addr < block_size);
980 if (split_addr > addr) {
981 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
987 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
988 RequestPtr sreqHigh, uint64_t *res,
991 translationStarted(true);
993 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
994 WholeTranslationState *state =
995 new WholeTranslationState(req, NULL, res, mode);
997 // One translation if the request isn't split.
998 DataTranslation<BaseDynInstPtr> *trans =
999 new DataTranslation<BaseDynInstPtr>(this, state);
1001 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1003 if (!translationCompleted()) {
1004 // The translation isn't yet complete, so we can't possibly have a
1005 // fault. Overwrite any existing fault we might have from a previous
1006 // execution of this instruction (e.g. an uncachable load that
1007 // couldn't execute because it wasn't at the head of the ROB).
1010 // Save memory requests.
1011 savedReq = state->mainReq;
1012 savedSreqLow = state->sreqLow;
1013 savedSreqHigh = state->sreqHigh;
1016 WholeTranslationState *state =
1017 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1019 // Two translations when the request is split.
1020 DataTranslation<BaseDynInstPtr> *stransLow =
1021 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1022 DataTranslation<BaseDynInstPtr> *stransHigh =
1023 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1025 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1026 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1028 if (!translationCompleted()) {
1029 // The translation isn't yet complete, so we can't possibly have a
1030 // fault. Overwrite any existing fault we might have from a previous
1031 // execution of this instruction (e.g. an uncachable load that
1032 // couldn't execute because it wasn't at the head of the ROB).
1035 // Save memory requests.
1036 savedReq = state->mainReq;
1037 savedSreqLow = state->sreqLow;
1038 savedSreqHigh = state->sreqHigh;
1043 template<class Impl>
1045 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1047 fault = state->getFault();
1049 instFlags[IsUncacheable] = state->isUncacheable();
1051 if (fault == NoFault) {
1052 physEffAddr = state->getPaddr();
1053 memReqFlags = state->getFlags();
1055 if (state->mainReq->isCondSwap()) {
1057 state->mainReq->setExtraData(*state->res);
1061 state->deleteReqs();
1065 translationCompleted(true);
1068 #endif // __CPU_BASE_DYN_INST_HH__