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31 #ifndef __CPU_BASE_DYN_INST_HH__
32 #define __CPU_BASE_DYN_INST_HH__
38 #include "arch/faults.hh"
39 #include "base/fast_alloc.hh"
40 #include "base/trace.hh"
41 #include "config/full_system.hh"
42 #include "cpu/o3/comm.hh"
43 #include "cpu/exetrace.hh"
44 #include "cpu/inst_seq.hh"
45 #include "cpu/op_class.hh"
46 #include "cpu/static_inst.hh"
47 #include "mem/packet.hh"
48 #include "sim/system.hh"
52 * Defines a dynamic instruction context.
55 // Forward declaration.
59 class BaseDynInst : public FastAlloc, public RefCounted
62 // Typedef for the CPU.
63 typedef typename Impl::CPUType ImplCPU;
64 typedef typename ImplCPU::ImplState ImplState;
66 // Logical register index type.
67 typedef TheISA::RegIndex RegIndex;
68 // Integer register type.
69 typedef TheISA::IntReg IntReg;
70 // Floating point register type.
71 typedef TheISA::FloatReg FloatReg;
73 // The DynInstPtr type.
74 typedef typename Impl::DynInstPtr DynInstPtr;
76 // The list of instructions iterator type.
77 typedef typename std::list<DynInstPtr>::iterator ListIt;
80 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
81 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
84 /** The StaticInst used by this BaseDynInst. */
85 StaticInstPtr staticInst;
87 ////////////////////////////////////////////
89 // INSTRUCTION EXECUTION
91 ////////////////////////////////////////////
92 /** InstRecord that tracks this instructions. */
93 Trace::InstRecord *traceData;
95 void demapPage(Addr vaddr, uint64_t asn)
97 cpu->demapPage(vaddr, asn);
99 void demapInstPage(Addr vaddr, uint64_t asn)
101 cpu->demapPage(vaddr, asn);
103 void demapDataPage(Addr vaddr, uint64_t asn)
105 cpu->demapPage(vaddr, asn);
109 * Does a read to a given address.
110 * @param addr The address to read.
111 * @param data The read's data is written into this parameter.
112 * @param flags The request's flags.
113 * @return Returns any fault due to the read.
116 Fault read(Addr addr, T &data, unsigned flags);
118 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
119 int size, unsigned flags);
122 * Does a write to a given address.
123 * @param data The data to be written.
124 * @param addr The address to write to.
125 * @param flags The request's flags.
126 * @param res The result of the write (for load locked/store conditionals).
127 * @return Returns any fault due to the write.
130 Fault write(T data, Addr addr, unsigned flags,
133 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
134 int size, unsigned flags);
136 void prefetch(Addr addr, unsigned flags);
137 void writeHint(Addr addr, int size, unsigned flags);
138 Fault copySrcTranslate(Addr src);
139 Fault copy(Addr dest);
141 /** @todo: Consider making this private. */
143 /** The sequence number of the instruction. */
147 IqEntry, /// Instruction is in the IQ
148 RobEntry, /// Instruction is in the ROB
149 LsqEntry, /// Instruction is in the LSQ
150 Completed, /// Instruction has completed
151 ResultReady, /// Instruction has its result
152 CanIssue, /// Instruction can issue and execute
153 Issued, /// Instruction has issued
154 Executed, /// Instruction has executed
155 CanCommit, /// Instruction can commit
156 AtCommit, /// Instruction has reached commit
157 Committed, /// Instruction has committed
158 Squashed, /// Instruction is squashed
159 SquashedInIQ, /// Instruction is squashed in the IQ
160 SquashedInLSQ, /// Instruction is squashed in the LSQ
161 SquashedInROB, /// Instruction is squashed in the ROB
162 RecoverInst, /// Is a recover instruction
163 BlockingInst, /// Is a blocking instruction
164 ThreadsyncWait, /// Is a thread synchronization instruction
165 SerializeBefore, /// Needs to serialize on
166 /// instructions ahead of it
167 SerializeAfter, /// Needs to serialize instructions behind it
168 SerializeHandled, /// Serialization has been handled
172 /** The status of this BaseDynInst. Several bits can be set. */
173 std::bitset<NumStatus> status;
175 /** The thread this instruction is from. */
178 /** data address space ID, for loads & stores. */
181 /** How many source registers are ready. */
184 /** Pointer to the Impl's CPU object. */
187 /** Pointer to the thread state. */
190 /** The kind of fault this instruction has generated. */
193 /** Pointer to the data for the memory access. */
196 /** The effective virtual address (lds & stores only). */
199 /** Is the effective virtual address valid. */
202 /** The effective physical address. */
205 /** Effective virtual address for a copy source. */
208 /** Effective physical address for a copy source. */
209 Addr copySrcPhysEffAddr;
211 /** The memory request flags (from translation). */
212 unsigned memReqFlags;
220 /** The result of the instruction; assumes for now that there's only one
221 * destination register.
225 /** Records changes to result? */
228 /** PC of this instruction. */
231 /** Micro PC of this instruction. */
235 /** Next non-speculative PC. It is not filled in at fetch, but rather
236 * once the target of the branch is truly known (either decode or
241 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
244 /** Next non-speculative micro PC. */
247 /** Predicted next PC. */
250 /** Predicted next NPC. */
253 /** Predicted next microPC */
256 /** If this is a branch that was predicted taken */
261 /** Count of total number of dynamic instructions. */
262 static int instcount;
268 /** Whether or not the source register is ready.
269 * @todo: Not sure this should be here vs the derived class.
271 bool _readySrcRegIdx[MaxInstSrcRegs];
274 /** Flattened register index of the destination registers of this
277 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
279 /** Flattened register index of the source registers of this
282 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
284 /** Physical register index of the destination registers of this
287 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
289 /** Physical register index of the source registers of this
292 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
294 /** Physical register index of the previous producers of the
295 * architected destinations.
297 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
301 /** Returns the physical register index of the i'th destination
304 PhysRegIndex renamedDestRegIdx(int idx) const
306 return _destRegIdx[idx];
309 /** Returns the physical register index of the i'th source register. */
310 PhysRegIndex renamedSrcRegIdx(int idx) const
312 return _srcRegIdx[idx];
315 /** Returns the flattened register index of the i'th destination
318 TheISA::RegIndex flattenedDestRegIdx(int idx) const
320 return _flatDestRegIdx[idx];
323 /** Returns the flattened register index of the i'th source register */
324 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
326 return _flatSrcRegIdx[idx];
329 /** Returns the physical register index of the previous physical register
330 * that remapped to the same logical register index.
332 PhysRegIndex prevDestRegIdx(int idx) const
334 return _prevDestRegIdx[idx];
337 /** Renames a destination register to a physical register. Also records
338 * the previous physical register that the logical register mapped to.
340 void renameDestReg(int idx,
341 PhysRegIndex renamed_dest,
342 PhysRegIndex previous_rename)
344 _destRegIdx[idx] = renamed_dest;
345 _prevDestRegIdx[idx] = previous_rename;
348 /** Renames a source logical register to the physical register which
349 * has/will produce that logical register's result.
350 * @todo: add in whether or not the source register is ready.
352 void renameSrcReg(int idx, PhysRegIndex renamed_src)
354 _srcRegIdx[idx] = renamed_src;
357 /** Flattens a source architectural register index into a logical index.
359 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
361 _flatSrcRegIdx[idx] = flattened_src;
364 /** Flattens a destination architectural register index into a logical
367 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
369 _flatDestRegIdx[idx] = flattened_dest;
371 /** BaseDynInst constructor given a binary instruction.
372 * @param staticInst A StaticInstPtr to the underlying instruction.
373 * @param PC The PC of the instruction.
374 * @param pred_PC The predicted next PC.
375 * @param pred_NPC The predicted next NPC.
376 * @param seq_num The sequence number of the instruction.
377 * @param cpu Pointer to the instruction's CPU.
379 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
380 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
381 InstSeqNum seq_num, ImplCPU *cpu);
383 /** BaseDynInst constructor given a binary instruction.
384 * @param inst The binary instruction.
385 * @param PC The PC of the instruction.
386 * @param pred_PC The predicted next PC.
387 * @param pred_NPC The predicted next NPC.
388 * @param seq_num The sequence number of the instruction.
389 * @param cpu Pointer to the instruction's CPU.
391 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
392 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
393 InstSeqNum seq_num, ImplCPU *cpu);
395 /** BaseDynInst constructor given a StaticInst pointer.
396 * @param _staticInst The StaticInst for this BaseDynInst.
398 BaseDynInst(StaticInstPtr &_staticInst);
400 /** BaseDynInst destructor. */
404 /** Function to initialize variables in the constructors. */
408 /** Dumps out contents of this BaseDynInst. */
411 /** Dumps out contents of this BaseDynInst into given string. */
412 void dump(std::string &outstring);
414 /** Read this CPU's ID. */
415 int readCpuId() { return cpu->readCpuId(); }
417 /** Returns the fault type. */
418 Fault getFault() { return fault; }
420 /** Checks whether or not this instruction has had its branch target
421 * calculated yet. For now it is not utilized and is hacked to be
423 * @todo: Actually use this instruction.
425 bool doneTargCalc() { return false; }
427 /** Returns the next PC. This could be the speculative next PC if it is
428 * called prior to the actual branch target being calculated.
430 Addr readNextPC() { return nextPC; }
432 /** Returns the next NPC. This could be the speculative next NPC if it is
433 * called prior to the actual branch target being calculated.
437 #if ISA_HAS_DELAY_SLOT
440 return nextPC + sizeof(TheISA::MachInst);
444 Addr readNextMicroPC()
449 /** Set the predicted target of this current instruction. */
450 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
451 Addr predicted_MicroPC)
453 predPC = predicted_PC;
454 predNPC = predicted_NPC;
455 predMicroPC = predicted_MicroPC;
458 /** Returns the predicted PC immediately after the branch. */
459 Addr readPredPC() { return predPC; }
461 /** Returns the predicted PC two instructions after the branch */
462 Addr readPredNPC() { return predNPC; }
464 /** Returns the predicted micro PC after the branch */
465 Addr readPredMicroPC() { return predMicroPC; }
467 /** Returns whether the instruction was predicted taken or not. */
473 void setPredTaken(bool predicted_taken)
475 predTaken = predicted_taken;
478 /** Returns whether the instruction mispredicted. */
481 return readPredPC() != readNextPC() ||
482 readPredNPC() != readNextNPC() ||
483 readPredMicroPC() != readNextMicroPC();
487 // Instruction types. Forward checks to StaticInst object.
489 bool isNop() const { return staticInst->isNop(); }
490 bool isMemRef() const { return staticInst->isMemRef(); }
491 bool isLoad() const { return staticInst->isLoad(); }
492 bool isStore() const { return staticInst->isStore(); }
493 bool isStoreConditional() const
494 { return staticInst->isStoreConditional(); }
495 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
496 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
497 bool isCopy() const { return staticInst->isCopy(); }
498 bool isInteger() const { return staticInst->isInteger(); }
499 bool isFloating() const { return staticInst->isFloating(); }
500 bool isControl() const { return staticInst->isControl(); }
501 bool isCall() const { return staticInst->isCall(); }
502 bool isReturn() const { return staticInst->isReturn(); }
503 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
504 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
505 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
506 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
507 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
508 bool isThreadSync() const { return staticInst->isThreadSync(); }
509 bool isSerializing() const { return staticInst->isSerializing(); }
510 bool isSerializeBefore() const
511 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
512 bool isSerializeAfter() const
513 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
514 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
515 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
516 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
517 bool isQuiesce() const { return staticInst->isQuiesce(); }
518 bool isIprAccess() const { return staticInst->isIprAccess(); }
519 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
520 bool isSyscall() const { return staticInst->isSyscall(); }
521 bool isMacroop() const { return staticInst->isMacroop(); }
522 bool isMicroop() const { return staticInst->isMicroop(); }
523 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
524 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
525 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
526 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
528 /** Temporarily sets this instruction as a serialize before instruction. */
529 void setSerializeBefore() { status.set(SerializeBefore); }
531 /** Clears the serializeBefore part of this instruction. */
532 void clearSerializeBefore() { status.reset(SerializeBefore); }
534 /** Checks if this serializeBefore is only temporarily set. */
535 bool isTempSerializeBefore() { return status[SerializeBefore]; }
537 /** Temporarily sets this instruction as a serialize after instruction. */
538 void setSerializeAfter() { status.set(SerializeAfter); }
540 /** Clears the serializeAfter part of this instruction.*/
541 void clearSerializeAfter() { status.reset(SerializeAfter); }
543 /** Checks if this serializeAfter is only temporarily set. */
544 bool isTempSerializeAfter() { return status[SerializeAfter]; }
546 /** Sets the serialization part of this instruction as handled. */
547 void setSerializeHandled() { status.set(SerializeHandled); }
549 /** Checks if the serialization part of this instruction has been
550 * handled. This does not apply to the temporary serializing
551 * state; it only applies to this instruction's own permanent
554 bool isSerializeHandled() { return status[SerializeHandled]; }
556 /** Returns the opclass of this instruction. */
557 OpClass opClass() const { return staticInst->opClass(); }
559 /** Returns the branch target address. */
560 Addr branchTarget() const { return staticInst->branchTarget(PC); }
562 /** Returns the number of source registers. */
563 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
565 /** Returns the number of destination registers. */
566 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
568 // the following are used to track physical register usage
569 // for machines with separate int & FP reg files
570 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
571 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
573 /** Returns the logical register index of the i'th destination register. */
574 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
576 /** Returns the logical register index of the i'th source register. */
577 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
579 /** Returns the result of an integer instruction. */
580 uint64_t readIntResult() { return instResult.integer; }
582 /** Returns the result of a floating point instruction. */
583 float readFloatResult() { return (float)instResult.dbl; }
585 /** Returns the result of a floating point (double) instruction. */
586 double readDoubleResult() { return instResult.dbl; }
588 /** Records an integer register being set to a value. */
589 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
592 instResult.integer = val;
595 /** Records an fp register being set to a value. */
596 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
601 instResult.dbl = (double)val;
602 else if (width == 64)
603 instResult.dbl = val;
605 panic("Unsupported width!");
609 /** Records an fp register being set to a value. */
610 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
613 instResult.dbl = (double)val;
616 /** Records an fp register being set to an integer value. */
617 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
621 instResult.integer = val;
624 /** Records an fp register being set to an integer value. */
625 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
628 instResult.integer = val;
631 /** Records that one of the source registers is ready. */
632 void markSrcRegReady();
634 /** Marks a specific register as ready. */
635 void markSrcRegReady(RegIndex src_idx);
637 /** Returns if a source register is ready. */
638 bool isReadySrcRegIdx(int idx) const
640 return this->_readySrcRegIdx[idx];
643 /** Sets this instruction as completed. */
644 void setCompleted() { status.set(Completed); }
646 /** Returns whether or not this instruction is completed. */
647 bool isCompleted() const { return status[Completed]; }
649 /** Marks the result as ready. */
650 void setResultReady() { status.set(ResultReady); }
652 /** Returns whether or not the result is ready. */
653 bool isResultReady() const { return status[ResultReady]; }
655 /** Sets this instruction as ready to issue. */
656 void setCanIssue() { status.set(CanIssue); }
658 /** Returns whether or not this instruction is ready to issue. */
659 bool readyToIssue() const { return status[CanIssue]; }
661 /** Clears this instruction being able to issue. */
662 void clearCanIssue() { status.reset(CanIssue); }
664 /** Sets this instruction as issued from the IQ. */
665 void setIssued() { status.set(Issued); }
667 /** Returns whether or not this instruction has issued. */
668 bool isIssued() const { return status[Issued]; }
670 /** Clears this instruction as being issued. */
671 void clearIssued() { status.reset(Issued); }
673 /** Sets this instruction as executed. */
674 void setExecuted() { status.set(Executed); }
676 /** Returns whether or not this instruction has executed. */
677 bool isExecuted() const { return status[Executed]; }
679 /** Sets this instruction as ready to commit. */
680 void setCanCommit() { status.set(CanCommit); }
682 /** Clears this instruction as being ready to commit. */
683 void clearCanCommit() { status.reset(CanCommit); }
685 /** Returns whether or not this instruction is ready to commit. */
686 bool readyToCommit() const { return status[CanCommit]; }
688 void setAtCommit() { status.set(AtCommit); }
690 bool isAtCommit() { return status[AtCommit]; }
692 /** Sets this instruction as committed. */
693 void setCommitted() { status.set(Committed); }
695 /** Returns whether or not this instruction is committed. */
696 bool isCommitted() const { return status[Committed]; }
698 /** Sets this instruction as squashed. */
699 void setSquashed() { status.set(Squashed); }
701 /** Returns whether or not this instruction is squashed. */
702 bool isSquashed() const { return status[Squashed]; }
704 //Instruction Queue Entry
705 //-----------------------
706 /** Sets this instruction as a entry the IQ. */
707 void setInIQ() { status.set(IqEntry); }
709 /** Sets this instruction as a entry the IQ. */
710 void clearInIQ() { status.reset(IqEntry); }
712 /** Returns whether or not this instruction has issued. */
713 bool isInIQ() const { return status[IqEntry]; }
715 /** Sets this instruction as squashed in the IQ. */
716 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
718 /** Returns whether or not this instruction is squashed in the IQ. */
719 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
722 //Load / Store Queue Functions
723 //-----------------------
724 /** Sets this instruction as a entry the LSQ. */
725 void setInLSQ() { status.set(LsqEntry); }
727 /** Sets this instruction as a entry the LSQ. */
728 void removeInLSQ() { status.reset(LsqEntry); }
730 /** Returns whether or not this instruction is in the LSQ. */
731 bool isInLSQ() const { return status[LsqEntry]; }
733 /** Sets this instruction as squashed in the LSQ. */
734 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
736 /** Returns whether or not this instruction is squashed in the LSQ. */
737 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
740 //Reorder Buffer Functions
741 //-----------------------
742 /** Sets this instruction as a entry the ROB. */
743 void setInROB() { status.set(RobEntry); }
745 /** Sets this instruction as a entry the ROB. */
746 void clearInROB() { status.reset(RobEntry); }
748 /** Returns whether or not this instruction is in the ROB. */
749 bool isInROB() const { return status[RobEntry]; }
751 /** Sets this instruction as squashed in the ROB. */
752 void setSquashedInROB() { status.set(SquashedInROB); }
754 /** Returns whether or not this instruction is squashed in the ROB. */
755 bool isSquashedInROB() const { return status[SquashedInROB]; }
757 /** Read the PC of this instruction. */
758 const Addr readPC() const { return PC; }
760 /**Read the micro PC of this instruction. */
761 const Addr readMicroPC() const { return microPC; }
763 /** Set the next PC of this instruction (its actual target). */
764 void setNextPC(Addr val)
769 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
770 void setNextNPC(Addr val)
772 #if ISA_HAS_DELAY_SLOT
777 void setNextMicroPC(Addr val)
782 /** Sets the ASID. */
783 void setASID(short addr_space_id) { asid = addr_space_id; }
785 /** Sets the thread id. */
786 void setTid(unsigned tid) { threadNumber = tid; }
788 /** Sets the pointer to the thread state. */
789 void setThreadState(ImplState *state) { thread = state; }
791 /** Returns the thread context. */
792 ThreadContext *tcBase() { return thread->getTC(); }
795 /** Instruction effective address.
796 * @todo: Consider if this is necessary or not.
800 /** Whether or not the effective address calculation is completed.
801 * @todo: Consider if this is necessary or not.
805 /** Is this instruction's memory access uncacheable. */
808 /** Has this instruction generated a memory request. */
812 /** Sets the effective address. */
813 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
815 /** Returns the effective address. */
816 const Addr &getEA() const { return instEffAddr; }
818 /** Returns whether or not the eff. addr. calculation has been completed. */
819 bool doneEACalc() { return eaCalcDone; }
821 /** Returns whether or not the eff. addr. source registers are ready. */
824 /** Whether or not the memory operation is done. */
827 /** Is this instruction's memory access uncacheable. */
828 bool uncacheable() { return isUncacheable; }
830 /** Has this instruction generated a memory request. */
831 bool hasRequest() { return reqMade; }
834 /** Load queue index. */
837 /** Store queue index. */
840 /** Iterator pointing to this BaseDynInst in the list of all insts. */
843 /** Returns iterator to this instruction in the list of all insts. */
844 ListIt &getInstListIt() { return instListIt; }
846 /** Sets iterator for this instruction in the list of all insts. */
847 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
850 /** Returns the number of consecutive store conditional failures. */
851 unsigned readStCondFailures()
852 { return thread->storeCondFailures; }
854 /** Sets the number of consecutive store conditional failures. */
855 void setStCondFailures(unsigned sc_failures)
856 { thread->storeCondFailures = sc_failures; }
861 BaseDynInst<Impl>::translateDataReadAddr(Addr vaddr, Addr &paddr,
862 int size, unsigned flags)
865 traceData->setAddr(vaddr);
869 Request *req = new Request();
870 req->setVirt(asid, vaddr, size, flags, PC);
871 req->setThreadContext(thread->readCpuId(), threadNumber);
873 fault = cpu->translateDataReadReq(req, thread);
875 if (fault == NoFault)
876 paddr = req->getPaddr();
885 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
888 Request *req = new Request();
889 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
890 req->setThreadContext(thread->readCpuId(), threadNumber);
892 fault = cpu->translateDataReadReq(req, thread);
894 if (req->isUncacheable())
895 isUncacheable = true;
897 if (fault == NoFault) {
898 effAddr = req->getVaddr();
900 physEffAddr = req->getPaddr();
901 memReqFlags = req->getFlags();
904 if (cpu->system->memctrl->badaddr(physEffAddr)) {
905 fault = TheISA::genMachineCheckFault();
909 fault = cpu->read(req, data, lqIdx);
912 fault = cpu->read(req, data, lqIdx);
915 // Return a fixed value to keep simulation deterministic even
916 // along misspeculated paths.
919 // Commit will have to clean up whatever happened. Set this
920 // instruction as executed.
926 traceData->setAddr(addr);
927 traceData->setData(data);
935 BaseDynInst<Impl>::translateDataWriteAddr(Addr vaddr, Addr &paddr,
936 int size, unsigned flags)
939 traceData->setAddr(vaddr);
943 Request *req = new Request();
944 req->setVirt(asid, vaddr, size, flags, PC);
945 req->setThreadContext(thread->readCpuId(), threadNumber);
947 fault = cpu->translateDataWriteReq(req, thread);
949 if (fault == NoFault)
950 paddr = req->getPaddr();
959 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
962 traceData->setAddr(addr);
963 traceData->setData(data);
967 Request *req = new Request();
968 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
969 req->setThreadContext(thread->readCpuId(), threadNumber);
971 fault = cpu->translateDataWriteReq(req, thread);
973 if (req->isUncacheable())
974 isUncacheable = true;
976 if (fault == NoFault) {
977 effAddr = req->getVaddr();
979 physEffAddr = req->getPaddr();
980 memReqFlags = req->getFlags();
982 if (req->isCondSwap()) {
984 req->setExtraData(*res);
987 if (cpu->system->memctrl->badaddr(physEffAddr)) {
988 fault = TheISA::genMachineCheckFault();
990 fault = cpu->write(req, data, sqIdx);
993 fault = cpu->write(req, data, sqIdx);
1002 #endif // __CPU_BASE_DYN_INST_HH__