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31 #ifndef __CPU_BASE_DYN_INST_HH__
32 #define __CPU_BASE_DYN_INST_HH__
38 #include "arch/faults.hh"
39 #include "base/fast_alloc.hh"
40 #include "base/trace.hh"
41 #include "config/full_system.hh"
42 #include "cpu/exetrace.hh"
43 #include "cpu/inst_seq.hh"
44 #include "cpu/op_class.hh"
45 #include "cpu/static_inst.hh"
46 #include "mem/packet.hh"
47 #include "sim/system.hh"
51 * Defines a dynamic instruction context.
54 // Forward declaration.
58 class BaseDynInst : public FastAlloc, public RefCounted
61 // Typedef for the CPU.
62 typedef typename Impl::CPUType ImplCPU;
63 typedef typename ImplCPU::ImplState ImplState;
65 // Binary machine instruction type.
66 typedef TheISA::MachInst MachInst;
67 // Extended machine instruction type
68 typedef TheISA::ExtMachInst ExtMachInst;
69 // Logical register index type.
70 typedef TheISA::RegIndex RegIndex;
71 // Integer register type.
72 typedef TheISA::IntReg IntReg;
73 // Floating point register type.
74 typedef TheISA::FloatReg FloatReg;
76 // The DynInstPtr type.
77 typedef typename Impl::DynInstPtr DynInstPtr;
79 // The list of instructions iterator type.
80 typedef typename std::list<DynInstPtr>::iterator ListIt;
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
87 /** The StaticInst used by this BaseDynInst. */
88 StaticInstPtr staticInst;
90 ////////////////////////////////////////////
92 // INSTRUCTION EXECUTION
94 ////////////////////////////////////////////
95 /** InstRecord that tracks this instructions. */
96 Trace::InstRecord *traceData;
99 * Does a read to a given address.
100 * @param addr The address to read.
101 * @param data The read's data is written into this parameter.
102 * @param flags The request's flags.
103 * @return Returns any fault due to the read.
106 Fault read(Addr addr, T &data, unsigned flags);
109 * Does a write to a given address.
110 * @param data The data to be written.
111 * @param addr The address to write to.
112 * @param flags The request's flags.
113 * @param res The result of the write (for load locked/store conditionals).
114 * @return Returns any fault due to the write.
117 Fault write(T data, Addr addr, unsigned flags,
120 void prefetch(Addr addr, unsigned flags);
121 void writeHint(Addr addr, int size, unsigned flags);
122 Fault copySrcTranslate(Addr src);
123 Fault copy(Addr dest);
125 /** @todo: Consider making this private. */
127 /** The sequence number of the instruction. */
131 IqEntry, /// Instruction is in the IQ
132 RobEntry, /// Instruction is in the ROB
133 LsqEntry, /// Instruction is in the LSQ
134 Completed, /// Instruction has completed
135 ResultReady, /// Instruction has its result
136 CanIssue, /// Instruction can issue and execute
137 Issued, /// Instruction has issued
138 Executed, /// Instruction has executed
139 CanCommit, /// Instruction can commit
140 AtCommit, /// Instruction has reached commit
141 Committed, /// Instruction has committed
142 Squashed, /// Instruction is squashed
143 SquashedInIQ, /// Instruction is squashed in the IQ
144 SquashedInLSQ, /// Instruction is squashed in the LSQ
145 SquashedInROB, /// Instruction is squashed in the ROB
146 RecoverInst, /// Is a recover instruction
147 BlockingInst, /// Is a blocking instruction
148 ThreadsyncWait, /// Is a thread synchronization instruction
149 SerializeBefore, /// Needs to serialize on
150 /// instructions ahead of it
151 SerializeAfter, /// Needs to serialize instructions behind it
152 SerializeHandled, /// Serialization has been handled
156 /** The status of this BaseDynInst. Several bits can be set. */
157 std::bitset<NumStatus> status;
159 /** The thread this instruction is from. */
162 /** data address space ID, for loads & stores. */
165 /** How many source registers are ready. */
168 /** Pointer to the Impl's CPU object. */
171 /** Pointer to the thread state. */
174 /** The kind of fault this instruction has generated. */
177 /** The memory request. */
180 /** Pointer to the data for the memory access. */
183 /** The effective virtual address (lds & stores only). */
186 /** The effective physical address. */
189 /** Effective virtual address for a copy source. */
192 /** Effective physical address for a copy source. */
193 Addr copySrcPhysEffAddr;
195 /** The memory request flags (from translation). */
196 unsigned memReqFlags;
204 /** The result of the instruction; assumes for now that there's only one
205 * destination register.
209 /** PC of this instruction. */
212 /** Next non-speculative PC. It is not filled in at fetch, but rather
213 * once the target of the branch is truly known (either decode or
218 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
221 /** Predicted next PC. */
224 /** Count of total number of dynamic instructions. */
225 static int instcount;
231 /** Whether or not the source register is ready.
232 * @todo: Not sure this should be here vs the derived class.
234 bool _readySrcRegIdx[MaxInstSrcRegs];
237 /** BaseDynInst constructor given a binary instruction.
238 * @param inst The binary instruction.
239 * @param PC The PC of the instruction.
240 * @param pred_PC The predicted next PC.
241 * @param seq_num The sequence number of the instruction.
242 * @param cpu Pointer to the instruction's CPU.
244 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
247 /** BaseDynInst constructor given a StaticInst pointer.
248 * @param _staticInst The StaticInst for this BaseDynInst.
250 BaseDynInst(StaticInstPtr &_staticInst);
252 /** BaseDynInst destructor. */
256 /** Function to initialize variables in the constructors. */
260 /** Dumps out contents of this BaseDynInst. */
263 /** Dumps out contents of this BaseDynInst into given string. */
264 void dump(std::string &outstring);
266 /** Returns the fault type. */
267 Fault getFault() { return fault; }
269 /** Checks whether or not this instruction has had its branch target
270 * calculated yet. For now it is not utilized and is hacked to be
272 * @todo: Actually use this instruction.
274 bool doneTargCalc() { return false; }
276 /** Returns the next PC. This could be the speculative next PC if it is
277 * called prior to the actual branch target being calculated.
279 Addr readNextPC() { return nextPC; }
281 /** Returns the next NPC. This could be the speculative next NPC if it is
282 * called prior to the actual branch target being calculated.
284 Addr readNextNPC() { return nextNPC; }
286 /** Set the predicted target of this current instruction. */
287 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
289 /** Returns the predicted target of the branch. */
290 Addr readPredTarg() { return predPC; }
292 /** Returns whether the instruction was predicted taken or not. */
294 #if ISA_HAS_DELAY_SLOT
295 { return predPC != (nextPC + sizeof(MachInst)); }
297 { return predPC != (PC + sizeof(MachInst)); }
300 /** Returns whether the instruction mispredicted. */
302 #if ISA_HAS_DELAY_SLOT
303 { return predPC != nextNPC; }
305 { return predPC != nextPC; }
308 // Instruction types. Forward checks to StaticInst object.
310 bool isNop() const { return staticInst->isNop(); }
311 bool isMemRef() const { return staticInst->isMemRef(); }
312 bool isLoad() const { return staticInst->isLoad(); }
313 bool isStore() const { return staticInst->isStore(); }
314 bool isStoreConditional() const
315 { return staticInst->isStoreConditional(); }
316 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
317 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
318 bool isCopy() const { return staticInst->isCopy(); }
319 bool isInteger() const { return staticInst->isInteger(); }
320 bool isFloating() const { return staticInst->isFloating(); }
321 bool isControl() const { return staticInst->isControl(); }
322 bool isCall() const { return staticInst->isCall(); }
323 bool isReturn() const { return staticInst->isReturn(); }
324 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
325 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
326 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
327 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
328 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
329 bool isThreadSync() const { return staticInst->isThreadSync(); }
330 bool isSerializing() const { return staticInst->isSerializing(); }
331 bool isSerializeBefore() const
332 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
333 bool isSerializeAfter() const
334 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
335 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
336 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
337 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
338 bool isQuiesce() const { return staticInst->isQuiesce(); }
339 bool isIprAccess() const { return staticInst->isIprAccess(); }
340 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
342 /** Temporarily sets this instruction as a serialize before instruction. */
343 void setSerializeBefore() { status.set(SerializeBefore); }
345 /** Clears the serializeBefore part of this instruction. */
346 void clearSerializeBefore() { status.reset(SerializeBefore); }
348 /** Checks if this serializeBefore is only temporarily set. */
349 bool isTempSerializeBefore() { return status[SerializeBefore]; }
351 /** Temporarily sets this instruction as a serialize after instruction. */
352 void setSerializeAfter() { status.set(SerializeAfter); }
354 /** Clears the serializeAfter part of this instruction.*/
355 void clearSerializeAfter() { status.reset(SerializeAfter); }
357 /** Checks if this serializeAfter is only temporarily set. */
358 bool isTempSerializeAfter() { return status[SerializeAfter]; }
360 /** Sets the serialization part of this instruction as handled. */
361 void setSerializeHandled() { status.set(SerializeHandled); }
363 /** Checks if the serialization part of this instruction has been
364 * handled. This does not apply to the temporary serializing
365 * state; it only applies to this instruction's own permanent
368 bool isSerializeHandled() { return status[SerializeHandled]; }
370 /** Returns the opclass of this instruction. */
371 OpClass opClass() const { return staticInst->opClass(); }
373 /** Returns the branch target address. */
374 Addr branchTarget() const { return staticInst->branchTarget(PC); }
376 /** Returns the number of source registers. */
377 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
379 /** Returns the number of destination registers. */
380 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
382 // the following are used to track physical register usage
383 // for machines with separate int & FP reg files
384 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
385 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
387 /** Returns the logical register index of the i'th destination register. */
388 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
390 /** Returns the logical register index of the i'th source register. */
391 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
393 /** Returns the result of an integer instruction. */
394 uint64_t readIntResult() { return instResult.integer; }
396 /** Returns the result of a floating point instruction. */
397 float readFloatResult() { return (float)instResult.dbl; }
399 /** Returns the result of a floating point (double) instruction. */
400 double readDoubleResult() { return instResult.dbl; }
402 /** Records an integer register being set to a value. */
403 void setIntReg(const StaticInst *si, int idx, uint64_t val)
405 instResult.integer = val;
408 /** Records an fp register being set to a value. */
409 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
412 instResult.dbl = (double)val;
413 else if (width == 64)
414 instResult.dbl = val;
416 panic("Unsupported width!");
419 /** Records an fp register being set to a value. */
420 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
422 // instResult.fp = val;
423 instResult.dbl = (double)val;
426 /** Records an fp register being set to an integer value. */
427 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
429 instResult.integer = val;
432 /** Records an fp register being set to an integer value. */
433 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
435 instResult.integer = val;
438 /** Records that one of the source registers is ready. */
439 void markSrcRegReady();
441 /** Marks a specific register as ready. */
442 void markSrcRegReady(RegIndex src_idx);
444 /** Returns if a source register is ready. */
445 bool isReadySrcRegIdx(int idx) const
447 return this->_readySrcRegIdx[idx];
450 /** Sets this instruction as completed. */
451 void setCompleted() { status.set(Completed); }
453 /** Returns whether or not this instruction is completed. */
454 bool isCompleted() const { return status[Completed]; }
456 /** Marks the result as ready. */
457 void setResultReady() { status.set(ResultReady); }
459 /** Returns whether or not the result is ready. */
460 bool isResultReady() const { return status[ResultReady]; }
462 /** Sets this instruction as ready to issue. */
463 void setCanIssue() { status.set(CanIssue); }
465 /** Returns whether or not this instruction is ready to issue. */
466 bool readyToIssue() const { return status[CanIssue]; }
468 /** Sets this instruction as issued from the IQ. */
469 void setIssued() { status.set(Issued); }
471 /** Returns whether or not this instruction has issued. */
472 bool isIssued() const { return status[Issued]; }
474 /** Sets this instruction as executed. */
475 void setExecuted() { status.set(Executed); }
477 /** Returns whether or not this instruction has executed. */
478 bool isExecuted() const { return status[Executed]; }
480 /** Sets this instruction as ready to commit. */
481 void setCanCommit() { status.set(CanCommit); }
483 /** Clears this instruction as being ready to commit. */
484 void clearCanCommit() { status.reset(CanCommit); }
486 /** Returns whether or not this instruction is ready to commit. */
487 bool readyToCommit() const { return status[CanCommit]; }
489 void setAtCommit() { status.set(AtCommit); }
491 bool isAtCommit() { return status[AtCommit]; }
493 /** Sets this instruction as committed. */
494 void setCommitted() { status.set(Committed); }
496 /** Returns whether or not this instruction is committed. */
497 bool isCommitted() const { return status[Committed]; }
499 /** Sets this instruction as squashed. */
500 void setSquashed() { status.set(Squashed); }
502 /** Returns whether or not this instruction is squashed. */
503 bool isSquashed() const { return status[Squashed]; }
505 //Instruction Queue Entry
506 //-----------------------
507 /** Sets this instruction as a entry the IQ. */
508 void setInIQ() { status.set(IqEntry); }
510 /** Sets this instruction as a entry the IQ. */
511 void clearInIQ() { status.reset(IqEntry); }
513 /** Returns whether or not this instruction has issued. */
514 bool isInIQ() const { return status[IqEntry]; }
516 /** Sets this instruction as squashed in the IQ. */
517 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
519 /** Returns whether or not this instruction is squashed in the IQ. */
520 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
523 //Load / Store Queue Functions
524 //-----------------------
525 /** Sets this instruction as a entry the LSQ. */
526 void setInLSQ() { status.set(LsqEntry); }
528 /** Sets this instruction as a entry the LSQ. */
529 void removeInLSQ() { status.reset(LsqEntry); }
531 /** Returns whether or not this instruction is in the LSQ. */
532 bool isInLSQ() const { return status[LsqEntry]; }
534 /** Sets this instruction as squashed in the LSQ. */
535 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
537 /** Returns whether or not this instruction is squashed in the LSQ. */
538 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
541 //Reorder Buffer Functions
542 //-----------------------
543 /** Sets this instruction as a entry the ROB. */
544 void setInROB() { status.set(RobEntry); }
546 /** Sets this instruction as a entry the ROB. */
547 void clearInROB() { status.reset(RobEntry); }
549 /** Returns whether or not this instruction is in the ROB. */
550 bool isInROB() const { return status[RobEntry]; }
552 /** Sets this instruction as squashed in the ROB. */
553 void setSquashedInROB() { status.set(SquashedInROB); }
555 /** Returns whether or not this instruction is squashed in the ROB. */
556 bool isSquashedInROB() const { return status[SquashedInROB]; }
558 /** Read the PC of this instruction. */
559 const Addr readPC() const { return PC; }
561 /** Set the next PC of this instruction (its actual target). */
562 void setNextPC(uint64_t val)
567 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
568 void setNextNPC(uint64_t val)
573 /** Sets the ASID. */
574 void setASID(short addr_space_id) { asid = addr_space_id; }
576 /** Sets the thread id. */
577 void setTid(unsigned tid) { threadNumber = tid; }
579 /** Sets the pointer to the thread state. */
580 void setThreadState(ImplState *state) { thread = state; }
582 /** Returns the thread context. */
583 ThreadContext *tcBase() { return thread->getTC(); }
586 /** Instruction effective address.
587 * @todo: Consider if this is necessary or not.
591 /** Whether or not the effective address calculation is completed.
592 * @todo: Consider if this is necessary or not.
597 /** Sets the effective address. */
598 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
600 /** Returns the effective address. */
601 const Addr &getEA() const { return instEffAddr; }
603 /** Returns whether or not the eff. addr. calculation has been completed. */
604 bool doneEACalc() { return eaCalcDone; }
606 /** Returns whether or not the eff. addr. source registers are ready. */
609 /** Whether or not the memory operation is done. */
613 /** Load queue index. */
616 /** Store queue index. */
619 /** Iterator pointing to this BaseDynInst in the list of all insts. */
622 /** Returns iterator to this instruction in the list of all insts. */
623 ListIt &getInstListIt() { return instListIt; }
625 /** Sets iterator for this instruction in the list of all insts. */
626 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
632 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
634 // Sometimes reads will get retried, so they may come through here
638 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
639 req->setThreadContext(thread->readCpuId(), threadNumber);
641 assert(addr == req->getVaddr());
644 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
645 TheISA::VMPageSize) {
646 return TheISA::genAlignmentFault();
649 fault = cpu->translateDataReadReq(req, thread);
651 if (fault == NoFault) {
652 effAddr = req->getVaddr();
653 physEffAddr = req->getPaddr();
654 memReqFlags = req->getFlags();
657 if (cpu->system->memctrl->badaddr(physEffAddr)) {
658 fault = TheISA::genMachineCheckFault();
662 fault = cpu->read(req, data, lqIdx);
665 fault = cpu->read(req, data, lqIdx);
668 // Return a fixed value to keep simulation deterministic even
669 // along misspeculated paths.
672 // Commit will have to clean up whatever happened. Set this
673 // instruction as executed.
678 traceData->setAddr(addr);
679 traceData->setData(data);
688 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
691 traceData->setAddr(addr);
692 traceData->setData(data);
698 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
699 req->setThreadContext(thread->readCpuId(), threadNumber);
701 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
702 TheISA::VMPageSize) {
703 return TheISA::genAlignmentFault();
706 fault = cpu->translateDataWriteReq(req, thread);
708 if (fault == NoFault) {
709 effAddr = req->getVaddr();
710 physEffAddr = req->getPaddr();
711 memReqFlags = req->getFlags();
713 if (cpu->system->memctrl->badaddr(physEffAddr)) {
714 fault = TheISA::genMachineCheckFault();
716 fault = cpu->write(req, data, sqIdx);
719 fault = cpu->write(req, data, sqIdx);
724 // always return some result to keep misspeculated paths
725 // (which will ignore faults) deterministic
726 *res = (fault == NoFault) ? req->getScResult() : 0;
732 #endif // __CPU_BASE_DYN_INST_HH__