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31 #ifndef __CPU_BASE_DYN_INST_HH__
32 #define __CPU_BASE_DYN_INST_HH__
38 #include "arch/faults.hh"
39 #include "base/fast_alloc.hh"
40 #include "base/trace.hh"
41 #include "config/full_system.hh"
42 #include "cpu/o3/comm.hh"
43 #include "cpu/exetrace.hh"
44 #include "cpu/inst_seq.hh"
45 #include "cpu/op_class.hh"
46 #include "cpu/static_inst.hh"
47 #include "mem/packet.hh"
48 #include "sim/system.hh"
53 * Defines a dynamic instruction context.
56 // Forward declaration.
60 class BaseDynInst : public FastAlloc, public RefCounted
63 // Typedef for the CPU.
64 typedef typename Impl::CPUType ImplCPU;
65 typedef typename ImplCPU::ImplState ImplState;
67 // Logical register index type.
68 typedef TheISA::RegIndex RegIndex;
69 // Integer register type.
70 typedef TheISA::IntReg IntReg;
71 // Floating point register type.
72 typedef TheISA::FloatReg FloatReg;
74 // The DynInstPtr type.
75 typedef typename Impl::DynInstPtr DynInstPtr;
77 // The list of instructions iterator type.
78 typedef typename std::list<DynInstPtr>::iterator ListIt;
81 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
82 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
85 /** The StaticInst used by this BaseDynInst. */
86 StaticInstPtr staticInst;
88 ////////////////////////////////////////////
90 // INSTRUCTION EXECUTION
92 ////////////////////////////////////////////
93 /** InstRecord that tracks this instructions. */
94 Trace::InstRecord *traceData;
96 void demapPage(Addr vaddr, uint64_t asn)
98 cpu->demapPage(vaddr, asn);
100 void demapInstPage(Addr vaddr, uint64_t asn)
102 cpu->demapPage(vaddr, asn);
104 void demapDataPage(Addr vaddr, uint64_t asn)
106 cpu->demapPage(vaddr, asn);
110 * Does a read to a given address.
111 * @param addr The address to read.
112 * @param data The read's data is written into this parameter.
113 * @param flags The request's flags.
114 * @return Returns any fault due to the read.
117 Fault read(Addr addr, T &data, unsigned flags);
120 * Does a write to a given address.
121 * @param data The data to be written.
122 * @param addr The address to write to.
123 * @param flags The request's flags.
124 * @param res The result of the write (for load locked/store conditionals).
125 * @return Returns any fault due to the write.
128 Fault write(T data, Addr addr, unsigned flags,
131 void prefetch(Addr addr, unsigned flags);
132 void writeHint(Addr addr, int size, unsigned flags);
133 Fault copySrcTranslate(Addr src);
134 Fault copy(Addr dest);
136 /** @todo: Consider making this private. */
138 /** The sequence number of the instruction. */
142 IqEntry, /// Instruction is in the IQ
143 RobEntry, /// Instruction is in the ROB
144 LsqEntry, /// Instruction is in the LSQ
145 Completed, /// Instruction has completed
146 ResultReady, /// Instruction has its result
147 CanIssue, /// Instruction can issue and execute
148 Issued, /// Instruction has issued
149 Executed, /// Instruction has executed
150 CanCommit, /// Instruction can commit
151 AtCommit, /// Instruction has reached commit
152 Committed, /// Instruction has committed
153 Squashed, /// Instruction is squashed
154 SquashedInIQ, /// Instruction is squashed in the IQ
155 SquashedInLSQ, /// Instruction is squashed in the LSQ
156 SquashedInROB, /// Instruction is squashed in the ROB
157 RecoverInst, /// Is a recover instruction
158 BlockingInst, /// Is a blocking instruction
159 ThreadsyncWait, /// Is a thread synchronization instruction
160 SerializeBefore, /// Needs to serialize on
161 /// instructions ahead of it
162 SerializeAfter, /// Needs to serialize instructions behind it
163 SerializeHandled, /// Serialization has been handled
167 /** The status of this BaseDynInst. Several bits can be set. */
168 std::bitset<NumStatus> status;
170 /** The thread this instruction is from. */
171 ThreadID threadNumber;
173 /** data address space ID, for loads & stores. */
176 /** How many source registers are ready. */
179 /** Pointer to the Impl's CPU object. */
182 /** Pointer to the thread state. */
185 /** The kind of fault this instruction has generated. */
188 /** Pointer to the data for the memory access. */
191 /** The effective virtual address (lds & stores only). */
194 /** Is the effective virtual address valid. */
197 /** The effective physical address. */
200 /** Effective virtual address for a copy source. */
203 /** Effective physical address for a copy source. */
204 Addr copySrcPhysEffAddr;
206 /** The memory request flags (from translation). */
207 unsigned memReqFlags;
215 /** The result of the instruction; assumes for now that there's only one
216 * destination register.
220 /** Records changes to result? */
223 /** PC of this instruction. */
226 /** Micro PC of this instruction. */
230 /** Next non-speculative PC. It is not filled in at fetch, but rather
231 * once the target of the branch is truly known (either decode or
236 /** Next non-speculative NPC. Target PC for Mips or Sparc. */
239 /** Next non-speculative micro PC. */
242 /** Predicted next PC. */
245 /** Predicted next NPC. */
248 /** Predicted next microPC */
251 /** If this is a branch that was predicted taken */
260 /** Whether or not the source register is ready.
261 * @todo: Not sure this should be here vs the derived class.
263 bool _readySrcRegIdx[MaxInstSrcRegs];
266 /** Flattened register index of the destination registers of this
269 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
271 /** Flattened register index of the source registers of this
274 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
276 /** Physical register index of the destination registers of this
279 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
281 /** Physical register index of the source registers of this
284 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
286 /** Physical register index of the previous producers of the
287 * architected destinations.
289 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
293 /** Returns the physical register index of the i'th destination
296 PhysRegIndex renamedDestRegIdx(int idx) const
298 return _destRegIdx[idx];
301 /** Returns the physical register index of the i'th source register. */
302 PhysRegIndex renamedSrcRegIdx(int idx) const
304 return _srcRegIdx[idx];
307 /** Returns the flattened register index of the i'th destination
310 TheISA::RegIndex flattenedDestRegIdx(int idx) const
312 return _flatDestRegIdx[idx];
315 /** Returns the flattened register index of the i'th source register */
316 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
318 return _flatSrcRegIdx[idx];
321 /** Returns the physical register index of the previous physical register
322 * that remapped to the same logical register index.
324 PhysRegIndex prevDestRegIdx(int idx) const
326 return _prevDestRegIdx[idx];
329 /** Renames a destination register to a physical register. Also records
330 * the previous physical register that the logical register mapped to.
332 void renameDestReg(int idx,
333 PhysRegIndex renamed_dest,
334 PhysRegIndex previous_rename)
336 _destRegIdx[idx] = renamed_dest;
337 _prevDestRegIdx[idx] = previous_rename;
340 /** Renames a source logical register to the physical register which
341 * has/will produce that logical register's result.
342 * @todo: add in whether or not the source register is ready.
344 void renameSrcReg(int idx, PhysRegIndex renamed_src)
346 _srcRegIdx[idx] = renamed_src;
349 /** Flattens a source architectural register index into a logical index.
351 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
353 _flatSrcRegIdx[idx] = flattened_src;
356 /** Flattens a destination architectural register index into a logical
359 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
361 _flatDestRegIdx[idx] = flattened_dest;
363 /** BaseDynInst constructor given a binary instruction.
364 * @param staticInst A StaticInstPtr to the underlying instruction.
365 * @param PC The PC of the instruction.
366 * @param pred_PC The predicted next PC.
367 * @param pred_NPC The predicted next NPC.
368 * @param seq_num The sequence number of the instruction.
369 * @param cpu Pointer to the instruction's CPU.
371 BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
372 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
373 InstSeqNum seq_num, ImplCPU *cpu);
375 /** BaseDynInst constructor given a binary instruction.
376 * @param inst The binary instruction.
377 * @param PC The PC of the instruction.
378 * @param pred_PC The predicted next PC.
379 * @param pred_NPC The predicted next NPC.
380 * @param seq_num The sequence number of the instruction.
381 * @param cpu Pointer to the instruction's CPU.
383 BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
384 Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
385 InstSeqNum seq_num, ImplCPU *cpu);
387 /** BaseDynInst constructor given a StaticInst pointer.
388 * @param _staticInst The StaticInst for this BaseDynInst.
390 BaseDynInst(StaticInstPtr &_staticInst);
392 /** BaseDynInst destructor. */
396 /** Function to initialize variables in the constructors. */
400 /** Dumps out contents of this BaseDynInst. */
403 /** Dumps out contents of this BaseDynInst into given string. */
404 void dump(std::string &outstring);
406 /** Read this CPU's ID. */
407 int cpuId() { return cpu->cpuId(); }
409 /** Read this context's system-wide ID **/
410 int contextId() { return thread->contextId(); }
412 /** Returns the fault type. */
413 Fault getFault() { return fault; }
415 /** Checks whether or not this instruction has had its branch target
416 * calculated yet. For now it is not utilized and is hacked to be
418 * @todo: Actually use this instruction.
420 bool doneTargCalc() { return false; }
422 /** Returns the next PC. This could be the speculative next PC if it is
423 * called prior to the actual branch target being calculated.
425 Addr readNextPC() { return nextPC; }
427 /** Returns the next NPC. This could be the speculative next NPC if it is
428 * called prior to the actual branch target being calculated.
432 #if ISA_HAS_DELAY_SLOT
435 return nextPC + sizeof(TheISA::MachInst);
439 Addr readNextMicroPC()
444 /** Set the predicted target of this current instruction. */
445 void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
446 Addr predicted_MicroPC)
448 predPC = predicted_PC;
449 predNPC = predicted_NPC;
450 predMicroPC = predicted_MicroPC;
453 /** Returns the predicted PC immediately after the branch. */
454 Addr readPredPC() { return predPC; }
456 /** Returns the predicted PC two instructions after the branch */
457 Addr readPredNPC() { return predNPC; }
459 /** Returns the predicted micro PC after the branch */
460 Addr readPredMicroPC() { return predMicroPC; }
462 /** Returns whether the instruction was predicted taken or not. */
468 void setPredTaken(bool predicted_taken)
470 predTaken = predicted_taken;
473 /** Returns whether the instruction mispredicted. */
476 return readPredPC() != readNextPC() ||
477 readPredNPC() != readNextNPC() ||
478 readPredMicroPC() != readNextMicroPC();
482 // Instruction types. Forward checks to StaticInst object.
484 bool isNop() const { return staticInst->isNop(); }
485 bool isMemRef() const { return staticInst->isMemRef(); }
486 bool isLoad() const { return staticInst->isLoad(); }
487 bool isStore() const { return staticInst->isStore(); }
488 bool isStoreConditional() const
489 { return staticInst->isStoreConditional(); }
490 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
491 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
492 bool isCopy() const { return staticInst->isCopy(); }
493 bool isInteger() const { return staticInst->isInteger(); }
494 bool isFloating() const { return staticInst->isFloating(); }
495 bool isControl() const { return staticInst->isControl(); }
496 bool isCall() const { return staticInst->isCall(); }
497 bool isReturn() const { return staticInst->isReturn(); }
498 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
499 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
500 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
501 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
502 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
503 bool isThreadSync() const { return staticInst->isThreadSync(); }
504 bool isSerializing() const { return staticInst->isSerializing(); }
505 bool isSerializeBefore() const
506 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
507 bool isSerializeAfter() const
508 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
509 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
510 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
511 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
512 bool isQuiesce() const { return staticInst->isQuiesce(); }
513 bool isIprAccess() const { return staticInst->isIprAccess(); }
514 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
515 bool isSyscall() const { return staticInst->isSyscall(); }
516 bool isMacroop() const { return staticInst->isMacroop(); }
517 bool isMicroop() const { return staticInst->isMicroop(); }
518 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
519 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
520 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
521 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
523 /** Temporarily sets this instruction as a serialize before instruction. */
524 void setSerializeBefore() { status.set(SerializeBefore); }
526 /** Clears the serializeBefore part of this instruction. */
527 void clearSerializeBefore() { status.reset(SerializeBefore); }
529 /** Checks if this serializeBefore is only temporarily set. */
530 bool isTempSerializeBefore() { return status[SerializeBefore]; }
532 /** Temporarily sets this instruction as a serialize after instruction. */
533 void setSerializeAfter() { status.set(SerializeAfter); }
535 /** Clears the serializeAfter part of this instruction.*/
536 void clearSerializeAfter() { status.reset(SerializeAfter); }
538 /** Checks if this serializeAfter is only temporarily set. */
539 bool isTempSerializeAfter() { return status[SerializeAfter]; }
541 /** Sets the serialization part of this instruction as handled. */
542 void setSerializeHandled() { status.set(SerializeHandled); }
544 /** Checks if the serialization part of this instruction has been
545 * handled. This does not apply to the temporary serializing
546 * state; it only applies to this instruction's own permanent
549 bool isSerializeHandled() { return status[SerializeHandled]; }
551 /** Returns the opclass of this instruction. */
552 OpClass opClass() const { return staticInst->opClass(); }
554 /** Returns the branch target address. */
555 Addr branchTarget() const { return staticInst->branchTarget(PC); }
557 /** Returns the number of source registers. */
558 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
560 /** Returns the number of destination registers. */
561 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
563 // the following are used to track physical register usage
564 // for machines with separate int & FP reg files
565 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
566 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
568 /** Returns the logical register index of the i'th destination register. */
569 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
571 /** Returns the logical register index of the i'th source register. */
572 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
574 /** Returns the result of an integer instruction. */
575 uint64_t readIntResult() { return instResult.integer; }
577 /** Returns the result of a floating point instruction. */
578 float readFloatResult() { return (float)instResult.dbl; }
580 /** Returns the result of a floating point (double) instruction. */
581 double readDoubleResult() { return instResult.dbl; }
583 /** Records an integer register being set to a value. */
584 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
587 instResult.integer = val;
590 /** Records an fp register being set to a value. */
591 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
596 instResult.dbl = (double)val;
597 else if (width == 64)
598 instResult.dbl = val;
600 panic("Unsupported width!");
604 /** Records an fp register being set to a value. */
605 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
608 instResult.dbl = (double)val;
611 /** Records an fp register being set to an integer value. */
612 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
616 instResult.integer = val;
619 /** Records an fp register being set to an integer value. */
620 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
623 instResult.integer = val;
626 /** Records that one of the source registers is ready. */
627 void markSrcRegReady();
629 /** Marks a specific register as ready. */
630 void markSrcRegReady(RegIndex src_idx);
632 /** Returns if a source register is ready. */
633 bool isReadySrcRegIdx(int idx) const
635 return this->_readySrcRegIdx[idx];
638 /** Sets this instruction as completed. */
639 void setCompleted() { status.set(Completed); }
641 /** Returns whether or not this instruction is completed. */
642 bool isCompleted() const { return status[Completed]; }
644 /** Marks the result as ready. */
645 void setResultReady() { status.set(ResultReady); }
647 /** Returns whether or not the result is ready. */
648 bool isResultReady() const { return status[ResultReady]; }
650 /** Sets this instruction as ready to issue. */
651 void setCanIssue() { status.set(CanIssue); }
653 /** Returns whether or not this instruction is ready to issue. */
654 bool readyToIssue() const { return status[CanIssue]; }
656 /** Clears this instruction being able to issue. */
657 void clearCanIssue() { status.reset(CanIssue); }
659 /** Sets this instruction as issued from the IQ. */
660 void setIssued() { status.set(Issued); }
662 /** Returns whether or not this instruction has issued. */
663 bool isIssued() const { return status[Issued]; }
665 /** Clears this instruction as being issued. */
666 void clearIssued() { status.reset(Issued); }
668 /** Sets this instruction as executed. */
669 void setExecuted() { status.set(Executed); }
671 /** Returns whether or not this instruction has executed. */
672 bool isExecuted() const { return status[Executed]; }
674 /** Sets this instruction as ready to commit. */
675 void setCanCommit() { status.set(CanCommit); }
677 /** Clears this instruction as being ready to commit. */
678 void clearCanCommit() { status.reset(CanCommit); }
680 /** Returns whether or not this instruction is ready to commit. */
681 bool readyToCommit() const { return status[CanCommit]; }
683 void setAtCommit() { status.set(AtCommit); }
685 bool isAtCommit() { return status[AtCommit]; }
687 /** Sets this instruction as committed. */
688 void setCommitted() { status.set(Committed); }
690 /** Returns whether or not this instruction is committed. */
691 bool isCommitted() const { return status[Committed]; }
693 /** Sets this instruction as squashed. */
694 void setSquashed() { status.set(Squashed); }
696 /** Returns whether or not this instruction is squashed. */
697 bool isSquashed() const { return status[Squashed]; }
699 //Instruction Queue Entry
700 //-----------------------
701 /** Sets this instruction as a entry the IQ. */
702 void setInIQ() { status.set(IqEntry); }
704 /** Sets this instruction as a entry the IQ. */
705 void clearInIQ() { status.reset(IqEntry); }
707 /** Returns whether or not this instruction has issued. */
708 bool isInIQ() const { return status[IqEntry]; }
710 /** Sets this instruction as squashed in the IQ. */
711 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
713 /** Returns whether or not this instruction is squashed in the IQ. */
714 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
717 //Load / Store Queue Functions
718 //-----------------------
719 /** Sets this instruction as a entry the LSQ. */
720 void setInLSQ() { status.set(LsqEntry); }
722 /** Sets this instruction as a entry the LSQ. */
723 void removeInLSQ() { status.reset(LsqEntry); }
725 /** Returns whether or not this instruction is in the LSQ. */
726 bool isInLSQ() const { return status[LsqEntry]; }
728 /** Sets this instruction as squashed in the LSQ. */
729 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
731 /** Returns whether or not this instruction is squashed in the LSQ. */
732 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
735 //Reorder Buffer Functions
736 //-----------------------
737 /** Sets this instruction as a entry the ROB. */
738 void setInROB() { status.set(RobEntry); }
740 /** Sets this instruction as a entry the ROB. */
741 void clearInROB() { status.reset(RobEntry); }
743 /** Returns whether or not this instruction is in the ROB. */
744 bool isInROB() const { return status[RobEntry]; }
746 /** Sets this instruction as squashed in the ROB. */
747 void setSquashedInROB() { status.set(SquashedInROB); }
749 /** Returns whether or not this instruction is squashed in the ROB. */
750 bool isSquashedInROB() const { return status[SquashedInROB]; }
752 /** Read the PC of this instruction. */
753 const Addr readPC() const { return PC; }
755 /**Read the micro PC of this instruction. */
756 const Addr readMicroPC() const { return microPC; }
758 /** Set the next PC of this instruction (its actual target). */
759 void setNextPC(Addr val)
764 /** Set the next NPC of this instruction (the target in Mips or Sparc).*/
765 void setNextNPC(Addr val)
767 #if ISA_HAS_DELAY_SLOT
772 void setNextMicroPC(Addr val)
777 /** Sets the ASID. */
778 void setASID(short addr_space_id) { asid = addr_space_id; }
780 /** Sets the thread id. */
781 void setTid(ThreadID tid) { threadNumber = tid; }
783 /** Sets the pointer to the thread state. */
784 void setThreadState(ImplState *state) { thread = state; }
786 /** Returns the thread context. */
787 ThreadContext *tcBase() { return thread->getTC(); }
790 /** Instruction effective address.
791 * @todo: Consider if this is necessary or not.
795 /** Whether or not the effective address calculation is completed.
796 * @todo: Consider if this is necessary or not.
800 /** Is this instruction's memory access uncacheable. */
803 /** Has this instruction generated a memory request. */
807 /** Sets the effective address. */
808 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
810 /** Returns the effective address. */
811 const Addr &getEA() const { return instEffAddr; }
813 /** Returns whether or not the eff. addr. calculation has been completed. */
814 bool doneEACalc() { return eaCalcDone; }
816 /** Returns whether or not the eff. addr. source registers are ready. */
819 /** Whether or not the memory operation is done. */
822 /** Is this instruction's memory access uncacheable. */
823 bool uncacheable() { return isUncacheable; }
825 /** Has this instruction generated a memory request. */
826 bool hasRequest() { return reqMade; }
829 /** Load queue index. */
832 /** Store queue index. */
835 /** Iterator pointing to this BaseDynInst in the list of all insts. */
838 /** Returns iterator to this instruction in the list of all insts. */
839 ListIt &getInstListIt() { return instListIt; }
841 /** Sets iterator for this instruction in the list of all insts. */
842 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
845 /** Returns the number of consecutive store conditional failures. */
846 unsigned readStCondFailures()
847 { return thread->storeCondFailures; }
849 /** Sets the number of consecutive store conditional failures. */
850 void setStCondFailures(unsigned sc_failures)
851 { thread->storeCondFailures = sc_failures; }
857 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
860 Request *req = new Request();
861 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
862 req->setThreadContext(thread->contextId(), threadNumber);
864 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
866 if (req->isUncacheable())
867 isUncacheable = true;
869 if (fault == NoFault) {
870 effAddr = req->getVaddr();
872 physEffAddr = req->getPaddr();
873 memReqFlags = req->getFlags();
876 if (cpu->system->memctrl->badaddr(physEffAddr)) {
877 fault = TheISA::genMachineCheckFault();
881 fault = cpu->read(req, data, lqIdx);
884 fault = cpu->read(req, data, lqIdx);
887 // Return a fixed value to keep simulation deterministic even
888 // along misspeculated paths.
891 // Commit will have to clean up whatever happened. Set this
892 // instruction as executed.
898 traceData->setAddr(addr);
899 traceData->setData(data);
908 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
911 traceData->setAddr(addr);
912 traceData->setData(data);
916 Request *req = new Request();
917 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
918 req->setThreadContext(thread->contextId(), threadNumber);
920 fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
922 if (req->isUncacheable())
923 isUncacheable = true;
925 if (fault == NoFault) {
926 effAddr = req->getVaddr();
928 physEffAddr = req->getPaddr();
929 memReqFlags = req->getFlags();
931 if (req->isCondSwap()) {
933 req->setExtraData(*res);
936 if (cpu->system->memctrl->badaddr(physEffAddr)) {
937 fault = TheISA::genMachineCheckFault();
939 fault = cpu->write(req, data, sqIdx);
942 fault = cpu->write(req, data, sqIdx);
951 #endif // __CPU_BASE_DYN_INST_HH__