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45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
52 #include "arch/faults.hh"
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/full_system.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/system.hh"
71 * Defines a dynamic instruction context.
74 // Forward declaration.
78 class BaseDynInst : public FastAlloc, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
92 // The DynInstPtr type.
93 typedef typename Impl::DynInstPtr DynInstPtr;
94 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
96 // The list of instructions iterator type.
97 typedef typename std::list<DynInstPtr>::iterator ListIt;
100 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
101 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
104 /** The StaticInst used by this BaseDynInst. */
105 StaticInstPtr staticInst;
107 ////////////////////////////////////////////
109 // INSTRUCTION EXECUTION
111 ////////////////////////////////////////////
112 /** InstRecord that tracks this instructions. */
113 Trace::InstRecord *traceData;
115 void demapPage(Addr vaddr, uint64_t asn)
117 cpu->demapPage(vaddr, asn);
119 void demapInstPage(Addr vaddr, uint64_t asn)
121 cpu->demapPage(vaddr, asn);
123 void demapDataPage(Addr vaddr, uint64_t asn)
125 cpu->demapPage(vaddr, asn);
128 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
130 Fault writeMem(uint8_t *data, unsigned size,
131 Addr addr, unsigned flags, uint64_t *res);
133 /** Splits a request in two if it crosses a dcache block. */
134 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
135 RequestPtr &sreqHigh);
137 /** Initiate a DTB address translation. */
138 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
139 RequestPtr sreqHigh, uint64_t *res,
142 /** Finish a DTB address translation. */
143 void finishTranslation(WholeTranslationState *state);
145 /** True if the DTB address translation has started. */
146 bool translationStarted;
148 /** True if the DTB address translation has completed. */
149 bool translationCompleted;
152 * Returns true if the DTB address translation is being delayed due to a hw
155 bool isTranslationDelayed() const
157 return (translationStarted && !translationCompleted);
161 * Saved memory requests (needed when the DTB address translation is
162 * delayed due to a hw page table walk).
165 RequestPtr savedSreqLow;
166 RequestPtr savedSreqHigh;
168 /** @todo: Consider making this private. */
170 /** The sequence number of the instruction. */
174 IqEntry, /// Instruction is in the IQ
175 RobEntry, /// Instruction is in the ROB
176 LsqEntry, /// Instruction is in the LSQ
177 Completed, /// Instruction has completed
178 ResultReady, /// Instruction has its result
179 CanIssue, /// Instruction can issue and execute
180 Issued, /// Instruction has issued
181 Executed, /// Instruction has executed
182 CanCommit, /// Instruction can commit
183 AtCommit, /// Instruction has reached commit
184 Committed, /// Instruction has committed
185 Squashed, /// Instruction is squashed
186 SquashedInIQ, /// Instruction is squashed in the IQ
187 SquashedInLSQ, /// Instruction is squashed in the LSQ
188 SquashedInROB, /// Instruction is squashed in the ROB
189 RecoverInst, /// Is a recover instruction
190 BlockingInst, /// Is a blocking instruction
191 ThreadsyncWait, /// Is a thread synchronization instruction
192 SerializeBefore, /// Needs to serialize on
193 /// instructions ahead of it
194 SerializeAfter, /// Needs to serialize instructions behind it
195 SerializeHandled, /// Serialization has been handled
199 /** The status of this BaseDynInst. Several bits can be set. */
200 std::bitset<NumStatus> status;
202 /** The thread this instruction is from. */
203 ThreadID threadNumber;
205 /** data address space ID, for loads & stores. */
208 /** How many source registers are ready. */
211 /** Pointer to the Impl's CPU object. */
214 /** Pointer to the thread state. */
217 /** The kind of fault this instruction has generated. */
220 /** Pointer to the data for the memory access. */
223 /** The effective virtual address (lds & stores only). */
226 /** The size of the request */
229 /** Is the effective virtual address valid. */
232 /** The effective physical address. */
235 /** The memory request flags (from translation). */
236 unsigned memReqFlags;
244 /** The result of the instruction; assumes for now that there's only one
245 * destination register.
249 /** Records changes to result? */
252 /** Did this instruction execute, or is it predicated false */
256 /** PC state for this instruction. */
259 /** Predicted PC state after this instruction. */
260 TheISA::PCState predPC;
262 /** If this is a branch that was predicted taken */
271 /** Whether or not the source register is ready.
272 * @todo: Not sure this should be here vs the derived class.
274 bool _readySrcRegIdx[MaxInstSrcRegs];
277 /** Flattened register index of the destination registers of this
280 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
282 /** Flattened register index of the source registers of this
285 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
287 /** Physical register index of the destination registers of this
290 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
292 /** Physical register index of the source registers of this
295 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
297 /** Physical register index of the previous producers of the
298 * architected destinations.
300 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
304 /** Returns the physical register index of the i'th destination
307 PhysRegIndex renamedDestRegIdx(int idx) const
309 return _destRegIdx[idx];
312 /** Returns the physical register index of the i'th source register. */
313 PhysRegIndex renamedSrcRegIdx(int idx) const
315 return _srcRegIdx[idx];
318 /** Returns the flattened register index of the i'th destination
321 TheISA::RegIndex flattenedDestRegIdx(int idx) const
323 return _flatDestRegIdx[idx];
326 /** Returns the flattened register index of the i'th source register */
327 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
329 return _flatSrcRegIdx[idx];
332 /** Returns the physical register index of the previous physical register
333 * that remapped to the same logical register index.
335 PhysRegIndex prevDestRegIdx(int idx) const
337 return _prevDestRegIdx[idx];
340 /** Renames a destination register to a physical register. Also records
341 * the previous physical register that the logical register mapped to.
343 void renameDestReg(int idx,
344 PhysRegIndex renamed_dest,
345 PhysRegIndex previous_rename)
347 _destRegIdx[idx] = renamed_dest;
348 _prevDestRegIdx[idx] = previous_rename;
351 /** Renames a source logical register to the physical register which
352 * has/will produce that logical register's result.
353 * @todo: add in whether or not the source register is ready.
355 void renameSrcReg(int idx, PhysRegIndex renamed_src)
357 _srcRegIdx[idx] = renamed_src;
360 /** Flattens a source architectural register index into a logical index.
362 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
364 _flatSrcRegIdx[idx] = flattened_src;
367 /** Flattens a destination architectural register index into a logical
370 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
372 _flatDestRegIdx[idx] = flattened_dest;
374 /** BaseDynInst constructor given a binary instruction.
375 * @param staticInst A StaticInstPtr to the underlying instruction.
376 * @param pc The PC state for the instruction.
377 * @param predPC The predicted next PC state for the instruction.
378 * @param seq_num The sequence number of the instruction.
379 * @param cpu Pointer to the instruction's CPU.
381 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
382 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
384 /** BaseDynInst constructor given a StaticInst pointer.
385 * @param _staticInst The StaticInst for this BaseDynInst.
387 BaseDynInst(StaticInstPtr &_staticInst);
389 /** BaseDynInst destructor. */
393 /** Function to initialize variables in the constructors. */
397 /** Dumps out contents of this BaseDynInst. */
400 /** Dumps out contents of this BaseDynInst into given string. */
401 void dump(std::string &outstring);
403 /** Read this CPU's ID. */
404 int cpuId() { return cpu->cpuId(); }
406 /** Read this context's system-wide ID **/
407 int contextId() { return thread->contextId(); }
409 /** Returns the fault type. */
410 Fault getFault() { return fault; }
412 /** Checks whether or not this instruction has had its branch target
413 * calculated yet. For now it is not utilized and is hacked to be
415 * @todo: Actually use this instruction.
417 bool doneTargCalc() { return false; }
419 /** Set the predicted target of this current instruction. */
420 void setPredTarg(const TheISA::PCState &_predPC)
425 const TheISA::PCState &readPredTarg() { return predPC; }
427 /** Returns the predicted PC immediately after the branch. */
428 Addr predInstAddr() { return predPC.instAddr(); }
430 /** Returns the predicted PC two instructions after the branch */
431 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
433 /** Returns the predicted micro PC after the branch */
434 Addr predMicroPC() { return predPC.microPC(); }
436 /** Returns whether the instruction was predicted taken or not. */
442 void setPredTaken(bool predicted_taken)
444 predTaken = predicted_taken;
447 /** Returns whether the instruction mispredicted. */
450 TheISA::PCState tempPC = pc;
451 TheISA::advancePC(tempPC, staticInst);
452 return !(tempPC == predPC);
456 // Instruction types. Forward checks to StaticInst object.
458 bool isNop() const { return staticInst->isNop(); }
459 bool isMemRef() const { return staticInst->isMemRef(); }
460 bool isLoad() const { return staticInst->isLoad(); }
461 bool isStore() const { return staticInst->isStore(); }
462 bool isStoreConditional() const
463 { return staticInst->isStoreConditional(); }
464 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
465 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
466 bool isInteger() const { return staticInst->isInteger(); }
467 bool isFloating() const { return staticInst->isFloating(); }
468 bool isControl() const { return staticInst->isControl(); }
469 bool isCall() const { return staticInst->isCall(); }
470 bool isReturn() const { return staticInst->isReturn(); }
471 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
472 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
473 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
474 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
475 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
476 bool isThreadSync() const { return staticInst->isThreadSync(); }
477 bool isSerializing() const { return staticInst->isSerializing(); }
478 bool isSerializeBefore() const
479 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
480 bool isSerializeAfter() const
481 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
482 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
483 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
484 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
485 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
486 bool isQuiesce() const { return staticInst->isQuiesce(); }
487 bool isIprAccess() const { return staticInst->isIprAccess(); }
488 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
489 bool isSyscall() const { return staticInst->isSyscall(); }
490 bool isMacroop() const { return staticInst->isMacroop(); }
491 bool isMicroop() const { return staticInst->isMicroop(); }
492 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
493 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
494 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
495 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
497 /** Temporarily sets this instruction as a serialize before instruction. */
498 void setSerializeBefore() { status.set(SerializeBefore); }
500 /** Clears the serializeBefore part of this instruction. */
501 void clearSerializeBefore() { status.reset(SerializeBefore); }
503 /** Checks if this serializeBefore is only temporarily set. */
504 bool isTempSerializeBefore() { return status[SerializeBefore]; }
506 /** Temporarily sets this instruction as a serialize after instruction. */
507 void setSerializeAfter() { status.set(SerializeAfter); }
509 /** Clears the serializeAfter part of this instruction.*/
510 void clearSerializeAfter() { status.reset(SerializeAfter); }
512 /** Checks if this serializeAfter is only temporarily set. */
513 bool isTempSerializeAfter() { return status[SerializeAfter]; }
515 /** Sets the serialization part of this instruction as handled. */
516 void setSerializeHandled() { status.set(SerializeHandled); }
518 /** Checks if the serialization part of this instruction has been
519 * handled. This does not apply to the temporary serializing
520 * state; it only applies to this instruction's own permanent
523 bool isSerializeHandled() { return status[SerializeHandled]; }
525 /** Returns the opclass of this instruction. */
526 OpClass opClass() const { return staticInst->opClass(); }
528 /** Returns the branch target address. */
529 TheISA::PCState branchTarget() const
530 { return staticInst->branchTarget(pc); }
532 /** Returns the number of source registers. */
533 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
535 /** Returns the number of destination registers. */
536 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
538 // the following are used to track physical register usage
539 // for machines with separate int & FP reg files
540 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
541 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
543 /** Returns the logical register index of the i'th destination register. */
544 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
546 /** Returns the logical register index of the i'th source register. */
547 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
549 /** Returns the result of an integer instruction. */
550 uint64_t readIntResult() { return instResult.integer; }
552 /** Returns the result of a floating point instruction. */
553 float readFloatResult() { return (float)instResult.dbl; }
555 /** Returns the result of a floating point (double) instruction. */
556 double readDoubleResult() { return instResult.dbl; }
558 /** Records an integer register being set to a value. */
559 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
562 instResult.integer = val;
565 /** Records an fp register being set to a value. */
566 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
571 instResult.dbl = (double)val;
572 else if (width == 64)
573 instResult.dbl = val;
575 panic("Unsupported width!");
579 /** Records an fp register being set to a value. */
580 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
583 instResult.dbl = (double)val;
586 /** Records an fp register being set to an integer value. */
587 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
591 instResult.integer = val;
594 /** Records an fp register being set to an integer value. */
595 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
598 instResult.integer = val;
601 /** Records that one of the source registers is ready. */
602 void markSrcRegReady();
604 /** Marks a specific register as ready. */
605 void markSrcRegReady(RegIndex src_idx);
607 /** Returns if a source register is ready. */
608 bool isReadySrcRegIdx(int idx) const
610 return this->_readySrcRegIdx[idx];
613 /** Sets this instruction as completed. */
614 void setCompleted() { status.set(Completed); }
616 /** Returns whether or not this instruction is completed. */
617 bool isCompleted() const { return status[Completed]; }
619 /** Marks the result as ready. */
620 void setResultReady() { status.set(ResultReady); }
622 /** Returns whether or not the result is ready. */
623 bool isResultReady() const { return status[ResultReady]; }
625 /** Sets this instruction as ready to issue. */
626 void setCanIssue() { status.set(CanIssue); }
628 /** Returns whether or not this instruction is ready to issue. */
629 bool readyToIssue() const { return status[CanIssue]; }
631 /** Clears this instruction being able to issue. */
632 void clearCanIssue() { status.reset(CanIssue); }
634 /** Sets this instruction as issued from the IQ. */
635 void setIssued() { status.set(Issued); }
637 /** Returns whether or not this instruction has issued. */
638 bool isIssued() const { return status[Issued]; }
640 /** Clears this instruction as being issued. */
641 void clearIssued() { status.reset(Issued); }
643 /** Sets this instruction as executed. */
644 void setExecuted() { status.set(Executed); }
646 /** Returns whether or not this instruction has executed. */
647 bool isExecuted() const { return status[Executed]; }
649 /** Sets this instruction as ready to commit. */
650 void setCanCommit() { status.set(CanCommit); }
652 /** Clears this instruction as being ready to commit. */
653 void clearCanCommit() { status.reset(CanCommit); }
655 /** Returns whether or not this instruction is ready to commit. */
656 bool readyToCommit() const { return status[CanCommit]; }
658 void setAtCommit() { status.set(AtCommit); }
660 bool isAtCommit() { return status[AtCommit]; }
662 /** Sets this instruction as committed. */
663 void setCommitted() { status.set(Committed); }
665 /** Returns whether or not this instruction is committed. */
666 bool isCommitted() const { return status[Committed]; }
668 /** Sets this instruction as squashed. */
669 void setSquashed() { status.set(Squashed); }
671 /** Returns whether or not this instruction is squashed. */
672 bool isSquashed() const { return status[Squashed]; }
674 //Instruction Queue Entry
675 //-----------------------
676 /** Sets this instruction as a entry the IQ. */
677 void setInIQ() { status.set(IqEntry); }
679 /** Sets this instruction as a entry the IQ. */
680 void clearInIQ() { status.reset(IqEntry); }
682 /** Returns whether or not this instruction has issued. */
683 bool isInIQ() const { return status[IqEntry]; }
685 /** Sets this instruction as squashed in the IQ. */
686 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
688 /** Returns whether or not this instruction is squashed in the IQ. */
689 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
692 //Load / Store Queue Functions
693 //-----------------------
694 /** Sets this instruction as a entry the LSQ. */
695 void setInLSQ() { status.set(LsqEntry); }
697 /** Sets this instruction as a entry the LSQ. */
698 void removeInLSQ() { status.reset(LsqEntry); }
700 /** Returns whether or not this instruction is in the LSQ. */
701 bool isInLSQ() const { return status[LsqEntry]; }
703 /** Sets this instruction as squashed in the LSQ. */
704 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
706 /** Returns whether or not this instruction is squashed in the LSQ. */
707 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
710 //Reorder Buffer Functions
711 //-----------------------
712 /** Sets this instruction as a entry the ROB. */
713 void setInROB() { status.set(RobEntry); }
715 /** Sets this instruction as a entry the ROB. */
716 void clearInROB() { status.reset(RobEntry); }
718 /** Returns whether or not this instruction is in the ROB. */
719 bool isInROB() const { return status[RobEntry]; }
721 /** Sets this instruction as squashed in the ROB. */
722 void setSquashedInROB() { status.set(SquashedInROB); }
724 /** Returns whether or not this instruction is squashed in the ROB. */
725 bool isSquashedInROB() const { return status[SquashedInROB]; }
727 /** Read the PC state of this instruction. */
728 const TheISA::PCState pcState() const { return pc; }
730 /** Set the PC state of this instruction. */
731 const void pcState(const TheISA::PCState &val) { pc = val; }
733 /** Read the PC of this instruction. */
734 const Addr instAddr() const { return pc.instAddr(); }
736 /** Read the PC of the next instruction. */
737 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
739 /**Read the micro PC of this instruction. */
740 const Addr microPC() const { return pc.microPC(); }
747 void setPredicate(bool val)
752 traceData->setPredicate(val);
756 /** Sets the ASID. */
757 void setASID(short addr_space_id) { asid = addr_space_id; }
759 /** Sets the thread id. */
760 void setTid(ThreadID tid) { threadNumber = tid; }
762 /** Sets the pointer to the thread state. */
763 void setThreadState(ImplState *state) { thread = state; }
765 /** Returns the thread context. */
766 ThreadContext *tcBase() { return thread->getTC(); }
769 /** Instruction effective address.
770 * @todo: Consider if this is necessary or not.
774 /** Whether or not the effective address calculation is completed.
775 * @todo: Consider if this is necessary or not.
779 /** Is this instruction's memory access uncacheable. */
782 /** Has this instruction generated a memory request. */
786 /** Sets the effective address. */
787 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
789 /** Returns the effective address. */
790 const Addr &getEA() const { return instEffAddr; }
792 /** Returns whether or not the eff. addr. calculation has been completed. */
793 bool doneEACalc() { return eaCalcDone; }
795 /** Returns whether or not the eff. addr. source registers are ready. */
798 /** Whether or not the memory operation is done. */
801 /** Is this instruction's memory access uncacheable. */
802 bool uncacheable() { return isUncacheable; }
804 /** Has this instruction generated a memory request. */
805 bool hasRequest() { return reqMade; }
808 /** Load queue index. */
811 /** Store queue index. */
814 /** Iterator pointing to this BaseDynInst in the list of all insts. */
817 /** Returns iterator to this instruction in the list of all insts. */
818 ListIt &getInstListIt() { return instListIt; }
820 /** Sets iterator for this instruction in the list of all insts. */
821 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
824 /** Returns the number of consecutive store conditional failures. */
825 unsigned readStCondFailures()
826 { return thread->storeCondFailures; }
828 /** Sets the number of consecutive store conditional failures. */
829 void setStCondFailures(unsigned sc_failures)
830 { thread->storeCondFailures = sc_failures; }
835 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
836 unsigned size, unsigned flags)
840 Request *sreqLow = NULL;
841 Request *sreqHigh = NULL;
843 if (reqMade && translationStarted) {
845 sreqLow = savedSreqLow;
846 sreqHigh = savedSreqHigh;
848 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
849 thread->contextId(), threadNumber);
851 // Only split the request if the ISA supports unaligned accesses.
852 if (TheISA::HasUnalignedMemAcc) {
853 splitRequest(req, sreqLow, sreqHigh);
855 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
858 if (translationCompleted) {
859 if (fault == NoFault) {
860 effAddr = req->getVaddr();
863 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
865 // Commit will have to clean up whatever happened. Set this
866 // instruction as executed.
870 if (fault != NoFault) {
871 // Return a fixed value to keep simulation deterministic even
872 // along misspeculated paths.
879 traceData->setAddr(addr);
887 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
888 Addr addr, unsigned flags, uint64_t *res)
891 traceData->setAddr(addr);
896 Request *sreqLow = NULL;
897 Request *sreqHigh = NULL;
899 if (reqMade && translationStarted) {
901 sreqLow = savedSreqLow;
902 sreqHigh = savedSreqHigh;
904 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
905 thread->contextId(), threadNumber);
907 // Only split the request if the ISA supports unaligned accesses.
908 if (TheISA::HasUnalignedMemAcc) {
909 splitRequest(req, sreqLow, sreqHigh);
911 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
914 if (fault == NoFault && translationCompleted) {
915 effAddr = req->getVaddr();
918 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
926 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
927 RequestPtr &sreqHigh)
929 // Check to see if the request crosses the next level block boundary.
930 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
931 Addr addr = req->getVaddr();
932 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
933 assert(split_addr <= addr || split_addr - addr < block_size);
936 if (split_addr > addr) {
937 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
943 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
944 RequestPtr sreqHigh, uint64_t *res,
947 translationStarted = true;
949 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
950 WholeTranslationState *state =
951 new WholeTranslationState(req, NULL, res, mode);
953 // One translation if the request isn't split.
954 DataTranslation<BaseDynInstPtr> *trans =
955 new DataTranslation<BaseDynInstPtr>(this, state);
956 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
957 if (!translationCompleted) {
958 // Save memory requests.
959 savedReq = state->mainReq;
960 savedSreqLow = state->sreqLow;
961 savedSreqHigh = state->sreqHigh;
964 WholeTranslationState *state =
965 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
967 // Two translations when the request is split.
968 DataTranslation<BaseDynInstPtr> *stransLow =
969 new DataTranslation<BaseDynInstPtr>(this, state, 0);
970 DataTranslation<BaseDynInstPtr> *stransHigh =
971 new DataTranslation<BaseDynInstPtr>(this, state, 1);
973 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
974 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
975 if (!translationCompleted) {
976 // Save memory requests.
977 savedReq = state->mainReq;
978 savedSreqLow = state->sreqLow;
979 savedSreqHigh = state->sreqHigh;
986 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
988 fault = state->getFault();
990 if (state->isUncacheable())
991 isUncacheable = true;
993 if (fault == NoFault) {
994 physEffAddr = state->getPaddr();
995 memReqFlags = state->getFlags();
997 if (state->mainReq->isCondSwap()) {
999 state->mainReq->setExtraData(*state->res);
1003 state->deleteReqs();
1007 translationCompleted = true;
1010 #endif // __CPU_BASE_DYN_INST_HH__