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45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
52 #include "arch/faults.hh"
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/full_system.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/system.hh"
71 * Defines a dynamic instruction context.
74 // Forward declaration.
78 class BaseDynInst : public FastAlloc, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
85 // Logical register index type.
86 typedef TheISA::RegIndex RegIndex;
87 // Integer register type.
88 typedef TheISA::IntReg IntReg;
89 // Floating point register type.
90 typedef TheISA::FloatReg FloatReg;
92 // The DynInstPtr type.
93 typedef typename Impl::DynInstPtr DynInstPtr;
95 // The list of instructions iterator type.
96 typedef typename std::list<DynInstPtr>::iterator ListIt;
99 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
100 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
103 /** The StaticInst used by this BaseDynInst. */
104 StaticInstPtr staticInst;
106 ////////////////////////////////////////////
108 // INSTRUCTION EXECUTION
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
114 void demapPage(Addr vaddr, uint64_t asn)
116 cpu->demapPage(vaddr, asn);
118 void demapInstPage(Addr vaddr, uint64_t asn)
120 cpu->demapPage(vaddr, asn);
122 void demapDataPage(Addr vaddr, uint64_t asn)
124 cpu->demapPage(vaddr, asn);
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,
141 /** Finish a DTB address translation. */
142 void finishTranslation(WholeTranslationState *state);
144 /** True if the DTB address translation has started. */
145 bool translationStarted;
147 /** True if the DTB address translation has completed. */
148 bool translationCompleted;
151 * Returns true if the DTB address translation is being delayed due to a hw
154 bool isTranslationDelayed() const
156 return (translationStarted && !translationCompleted);
160 * Saved memory requests (needed when the DTB address translation is
161 * delayed due to a hw page table walk).
164 RequestPtr savedSreqLow;
165 RequestPtr savedSreqHigh;
167 /** @todo: Consider making this private. */
169 /** The sequence number of the instruction. */
173 IqEntry, /// Instruction is in the IQ
174 RobEntry, /// Instruction is in the ROB
175 LsqEntry, /// Instruction is in the LSQ
176 Completed, /// Instruction has completed
177 ResultReady, /// Instruction has its result
178 CanIssue, /// Instruction can issue and execute
179 Issued, /// Instruction has issued
180 Executed, /// Instruction has executed
181 CanCommit, /// Instruction can commit
182 AtCommit, /// Instruction has reached commit
183 Committed, /// Instruction has committed
184 Squashed, /// Instruction is squashed
185 SquashedInIQ, /// Instruction is squashed in the IQ
186 SquashedInLSQ, /// Instruction is squashed in the LSQ
187 SquashedInROB, /// Instruction is squashed in the ROB
188 RecoverInst, /// Is a recover instruction
189 BlockingInst, /// Is a blocking instruction
190 ThreadsyncWait, /// Is a thread synchronization instruction
191 SerializeBefore, /// Needs to serialize on
192 /// instructions ahead of it
193 SerializeAfter, /// Needs to serialize instructions behind it
194 SerializeHandled, /// Serialization has been handled
198 /** The status of this BaseDynInst. Several bits can be set. */
199 std::bitset<NumStatus> status;
201 /** The thread this instruction is from. */
202 ThreadID threadNumber;
204 /** data address space ID, for loads & stores. */
207 /** How many source registers are ready. */
210 /** Pointer to the Impl's CPU object. */
213 /** Pointer to the thread state. */
216 /** The kind of fault this instruction has generated. */
219 /** Pointer to the data for the memory access. */
222 /** The effective virtual address (lds & stores only). */
225 /** The size of the request */
228 /** Is the effective virtual address valid. */
231 /** The effective physical address. */
234 /** The memory request flags (from translation). */
235 unsigned memReqFlags;
243 /** The result of the instruction; assumes for now that there's only one
244 * destination register.
248 /** Records changes to result? */
251 /** Did this instruction execute, or is it predicated false */
255 /** PC state for this instruction. */
258 /** Predicted PC state after this instruction. */
259 TheISA::PCState predPC;
261 /** If this is a branch that was predicted taken */
270 /** Whether or not the source register is ready.
271 * @todo: Not sure this should be here vs the derived class.
273 bool _readySrcRegIdx[MaxInstSrcRegs];
276 /** Flattened register index of the destination registers of this
279 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
281 /** Flattened register index of the source registers of this
284 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
286 /** Physical register index of the destination registers of this
289 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
291 /** Physical register index of the source registers of this
294 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
296 /** Physical register index of the previous producers of the
297 * architected destinations.
299 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
303 /** Returns the physical register index of the i'th destination
306 PhysRegIndex renamedDestRegIdx(int idx) const
308 return _destRegIdx[idx];
311 /** Returns the physical register index of the i'th source register. */
312 PhysRegIndex renamedSrcRegIdx(int idx) const
314 return _srcRegIdx[idx];
317 /** Returns the flattened register index of the i'th destination
320 TheISA::RegIndex flattenedDestRegIdx(int idx) const
322 return _flatDestRegIdx[idx];
325 /** Returns the flattened register index of the i'th source register */
326 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
328 return _flatSrcRegIdx[idx];
331 /** Returns the physical register index of the previous physical register
332 * that remapped to the same logical register index.
334 PhysRegIndex prevDestRegIdx(int idx) const
336 return _prevDestRegIdx[idx];
339 /** Renames a destination register to a physical register. Also records
340 * the previous physical register that the logical register mapped to.
342 void renameDestReg(int idx,
343 PhysRegIndex renamed_dest,
344 PhysRegIndex previous_rename)
346 _destRegIdx[idx] = renamed_dest;
347 _prevDestRegIdx[idx] = previous_rename;
350 /** Renames a source logical register to the physical register which
351 * has/will produce that logical register's result.
352 * @todo: add in whether or not the source register is ready.
354 void renameSrcReg(int idx, PhysRegIndex renamed_src)
356 _srcRegIdx[idx] = renamed_src;
359 /** Flattens a source architectural register index into a logical index.
361 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
363 _flatSrcRegIdx[idx] = flattened_src;
366 /** Flattens a destination architectural register index into a logical
369 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
371 _flatDestRegIdx[idx] = flattened_dest;
373 /** BaseDynInst constructor given a binary instruction.
374 * @param staticInst A StaticInstPtr to the underlying instruction.
375 * @param pc The PC state for the instruction.
376 * @param predPC The predicted next PC state for the instruction.
377 * @param seq_num The sequence number of the instruction.
378 * @param cpu Pointer to the instruction's CPU.
380 BaseDynInst(StaticInstPtr staticInst, TheISA::PCState pc,
381 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
383 /** BaseDynInst constructor given a binary instruction.
384 * @param inst The binary instruction.
385 * @param _pc The PC state for the instruction.
386 * @param _predPC The predicted next PC state for the instruction.
387 * @param seq_num The sequence number of the instruction.
388 * @param cpu Pointer to the instruction's CPU.
390 BaseDynInst(TheISA::ExtMachInst inst, TheISA::PCState pc,
391 TheISA::PCState predPC, InstSeqNum seq_num, ImplCPU *cpu);
393 /** BaseDynInst constructor given a StaticInst pointer.
394 * @param _staticInst The StaticInst for this BaseDynInst.
396 BaseDynInst(StaticInstPtr &_staticInst);
398 /** BaseDynInst destructor. */
402 /** Function to initialize variables in the constructors. */
406 /** Dumps out contents of this BaseDynInst. */
409 /** Dumps out contents of this BaseDynInst into given string. */
410 void dump(std::string &outstring);
412 /** Read this CPU's ID. */
413 int cpuId() { return cpu->cpuId(); }
415 /** Read this context's system-wide ID **/
416 int contextId() { return thread->contextId(); }
418 /** Returns the fault type. */
419 Fault getFault() { return fault; }
421 /** Checks whether or not this instruction has had its branch target
422 * calculated yet. For now it is not utilized and is hacked to be
424 * @todo: Actually use this instruction.
426 bool doneTargCalc() { return false; }
428 /** Set the predicted target of this current instruction. */
429 void setPredTarg(const TheISA::PCState &_predPC)
434 const TheISA::PCState &readPredTarg() { return predPC; }
436 /** Returns the predicted PC immediately after the branch. */
437 Addr predInstAddr() { return predPC.instAddr(); }
439 /** Returns the predicted PC two instructions after the branch */
440 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
442 /** Returns the predicted micro PC after the branch */
443 Addr predMicroPC() { return predPC.microPC(); }
445 /** Returns whether the instruction was predicted taken or not. */
451 void setPredTaken(bool predicted_taken)
453 predTaken = predicted_taken;
456 /** Returns whether the instruction mispredicted. */
459 TheISA::PCState tempPC = pc;
460 TheISA::advancePC(tempPC, staticInst);
461 return !(tempPC == predPC);
465 // Instruction types. Forward checks to StaticInst object.
467 bool isNop() const { return staticInst->isNop(); }
468 bool isMemRef() const { return staticInst->isMemRef(); }
469 bool isLoad() const { return staticInst->isLoad(); }
470 bool isStore() const { return staticInst->isStore(); }
471 bool isStoreConditional() const
472 { return staticInst->isStoreConditional(); }
473 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
474 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
475 bool isInteger() const { return staticInst->isInteger(); }
476 bool isFloating() const { return staticInst->isFloating(); }
477 bool isControl() const { return staticInst->isControl(); }
478 bool isCall() const { return staticInst->isCall(); }
479 bool isReturn() const { return staticInst->isReturn(); }
480 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
481 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
482 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
483 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
484 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
485 bool isThreadSync() const { return staticInst->isThreadSync(); }
486 bool isSerializing() const { return staticInst->isSerializing(); }
487 bool isSerializeBefore() const
488 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
489 bool isSerializeAfter() const
490 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
491 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
492 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
493 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
494 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
495 bool isQuiesce() const { return staticInst->isQuiesce(); }
496 bool isIprAccess() const { return staticInst->isIprAccess(); }
497 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
498 bool isSyscall() const { return staticInst->isSyscall(); }
499 bool isMacroop() const { return staticInst->isMacroop(); }
500 bool isMicroop() const { return staticInst->isMicroop(); }
501 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
502 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
503 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
504 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
506 /** Temporarily sets this instruction as a serialize before instruction. */
507 void setSerializeBefore() { status.set(SerializeBefore); }
509 /** Clears the serializeBefore part of this instruction. */
510 void clearSerializeBefore() { status.reset(SerializeBefore); }
512 /** Checks if this serializeBefore is only temporarily set. */
513 bool isTempSerializeBefore() { return status[SerializeBefore]; }
515 /** Temporarily sets this instruction as a serialize after instruction. */
516 void setSerializeAfter() { status.set(SerializeAfter); }
518 /** Clears the serializeAfter part of this instruction.*/
519 void clearSerializeAfter() { status.reset(SerializeAfter); }
521 /** Checks if this serializeAfter is only temporarily set. */
522 bool isTempSerializeAfter() { return status[SerializeAfter]; }
524 /** Sets the serialization part of this instruction as handled. */
525 void setSerializeHandled() { status.set(SerializeHandled); }
527 /** Checks if the serialization part of this instruction has been
528 * handled. This does not apply to the temporary serializing
529 * state; it only applies to this instruction's own permanent
532 bool isSerializeHandled() { return status[SerializeHandled]; }
534 /** Returns the opclass of this instruction. */
535 OpClass opClass() const { return staticInst->opClass(); }
537 /** Returns the branch target address. */
538 TheISA::PCState branchTarget() const
539 { return staticInst->branchTarget(pc); }
541 /** Returns the number of source registers. */
542 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
544 /** Returns the number of destination registers. */
545 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
547 // the following are used to track physical register usage
548 // for machines with separate int & FP reg files
549 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
550 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
552 /** Returns the logical register index of the i'th destination register. */
553 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
555 /** Returns the logical register index of the i'th source register. */
556 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
558 /** Returns the result of an integer instruction. */
559 uint64_t readIntResult() { return instResult.integer; }
561 /** Returns the result of a floating point instruction. */
562 float readFloatResult() { return (float)instResult.dbl; }
564 /** Returns the result of a floating point (double) instruction. */
565 double readDoubleResult() { return instResult.dbl; }
567 /** Records an integer register being set to a value. */
568 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
571 instResult.integer = val;
574 /** Records an fp register being set to a value. */
575 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
580 instResult.dbl = (double)val;
581 else if (width == 64)
582 instResult.dbl = val;
584 panic("Unsupported width!");
588 /** Records an fp register being set to a value. */
589 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
592 instResult.dbl = (double)val;
595 /** Records an fp register being set to an integer value. */
596 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
600 instResult.integer = val;
603 /** Records an fp register being set to an integer value. */
604 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
607 instResult.integer = val;
610 /** Records that one of the source registers is ready. */
611 void markSrcRegReady();
613 /** Marks a specific register as ready. */
614 void markSrcRegReady(RegIndex src_idx);
616 /** Returns if a source register is ready. */
617 bool isReadySrcRegIdx(int idx) const
619 return this->_readySrcRegIdx[idx];
622 /** Sets this instruction as completed. */
623 void setCompleted() { status.set(Completed); }
625 /** Returns whether or not this instruction is completed. */
626 bool isCompleted() const { return status[Completed]; }
628 /** Marks the result as ready. */
629 void setResultReady() { status.set(ResultReady); }
631 /** Returns whether or not the result is ready. */
632 bool isResultReady() const { return status[ResultReady]; }
634 /** Sets this instruction as ready to issue. */
635 void setCanIssue() { status.set(CanIssue); }
637 /** Returns whether or not this instruction is ready to issue. */
638 bool readyToIssue() const { return status[CanIssue]; }
640 /** Clears this instruction being able to issue. */
641 void clearCanIssue() { status.reset(CanIssue); }
643 /** Sets this instruction as issued from the IQ. */
644 void setIssued() { status.set(Issued); }
646 /** Returns whether or not this instruction has issued. */
647 bool isIssued() const { return status[Issued]; }
649 /** Clears this instruction as being issued. */
650 void clearIssued() { status.reset(Issued); }
652 /** Sets this instruction as executed. */
653 void setExecuted() { status.set(Executed); }
655 /** Returns whether or not this instruction has executed. */
656 bool isExecuted() const { return status[Executed]; }
658 /** Sets this instruction as ready to commit. */
659 void setCanCommit() { status.set(CanCommit); }
661 /** Clears this instruction as being ready to commit. */
662 void clearCanCommit() { status.reset(CanCommit); }
664 /** Returns whether or not this instruction is ready to commit. */
665 bool readyToCommit() const { return status[CanCommit]; }
667 void setAtCommit() { status.set(AtCommit); }
669 bool isAtCommit() { return status[AtCommit]; }
671 /** Sets this instruction as committed. */
672 void setCommitted() { status.set(Committed); }
674 /** Returns whether or not this instruction is committed. */
675 bool isCommitted() const { return status[Committed]; }
677 /** Sets this instruction as squashed. */
678 void setSquashed() { status.set(Squashed); }
680 /** Returns whether or not this instruction is squashed. */
681 bool isSquashed() const { return status[Squashed]; }
683 //Instruction Queue Entry
684 //-----------------------
685 /** Sets this instruction as a entry the IQ. */
686 void setInIQ() { status.set(IqEntry); }
688 /** Sets this instruction as a entry the IQ. */
689 void clearInIQ() { status.reset(IqEntry); }
691 /** Returns whether or not this instruction has issued. */
692 bool isInIQ() const { return status[IqEntry]; }
694 /** Sets this instruction as squashed in the IQ. */
695 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
697 /** Returns whether or not this instruction is squashed in the IQ. */
698 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
701 //Load / Store Queue Functions
702 //-----------------------
703 /** Sets this instruction as a entry the LSQ. */
704 void setInLSQ() { status.set(LsqEntry); }
706 /** Sets this instruction as a entry the LSQ. */
707 void removeInLSQ() { status.reset(LsqEntry); }
709 /** Returns whether or not this instruction is in the LSQ. */
710 bool isInLSQ() const { return status[LsqEntry]; }
712 /** Sets this instruction as squashed in the LSQ. */
713 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
715 /** Returns whether or not this instruction is squashed in the LSQ. */
716 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
719 //Reorder Buffer Functions
720 //-----------------------
721 /** Sets this instruction as a entry the ROB. */
722 void setInROB() { status.set(RobEntry); }
724 /** Sets this instruction as a entry the ROB. */
725 void clearInROB() { status.reset(RobEntry); }
727 /** Returns whether or not this instruction is in the ROB. */
728 bool isInROB() const { return status[RobEntry]; }
730 /** Sets this instruction as squashed in the ROB. */
731 void setSquashedInROB() { status.set(SquashedInROB); }
733 /** Returns whether or not this instruction is squashed in the ROB. */
734 bool isSquashedInROB() const { return status[SquashedInROB]; }
736 /** Read the PC state of this instruction. */
737 const TheISA::PCState pcState() const { return pc; }
739 /** Set the PC state of this instruction. */
740 const void pcState(const TheISA::PCState &val) { pc = val; }
742 /** Read the PC of this instruction. */
743 const Addr instAddr() const { return pc.instAddr(); }
745 /** Read the PC of the next instruction. */
746 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
748 /**Read the micro PC of this instruction. */
749 const Addr microPC() const { return pc.microPC(); }
756 void setPredicate(bool val)
761 traceData->setPredicate(val);
765 /** Sets the ASID. */
766 void setASID(short addr_space_id) { asid = addr_space_id; }
768 /** Sets the thread id. */
769 void setTid(ThreadID tid) { threadNumber = tid; }
771 /** Sets the pointer to the thread state. */
772 void setThreadState(ImplState *state) { thread = state; }
774 /** Returns the thread context. */
775 ThreadContext *tcBase() { return thread->getTC(); }
778 /** Instruction effective address.
779 * @todo: Consider if this is necessary or not.
783 /** Whether or not the effective address calculation is completed.
784 * @todo: Consider if this is necessary or not.
788 /** Is this instruction's memory access uncacheable. */
791 /** Has this instruction generated a memory request. */
795 /** Sets the effective address. */
796 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
798 /** Returns the effective address. */
799 const Addr &getEA() const { return instEffAddr; }
801 /** Returns whether or not the eff. addr. calculation has been completed. */
802 bool doneEACalc() { return eaCalcDone; }
804 /** Returns whether or not the eff. addr. source registers are ready. */
807 /** Whether or not the memory operation is done. */
810 /** Is this instruction's memory access uncacheable. */
811 bool uncacheable() { return isUncacheable; }
813 /** Has this instruction generated a memory request. */
814 bool hasRequest() { return reqMade; }
817 /** Load queue index. */
820 /** Store queue index. */
823 /** Iterator pointing to this BaseDynInst in the list of all insts. */
826 /** Returns iterator to this instruction in the list of all insts. */
827 ListIt &getInstListIt() { return instListIt; }
829 /** Sets iterator for this instruction in the list of all insts. */
830 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
833 /** Returns the number of consecutive store conditional failures. */
834 unsigned readStCondFailures()
835 { return thread->storeCondFailures; }
837 /** Sets the number of consecutive store conditional failures. */
838 void setStCondFailures(unsigned sc_failures)
839 { thread->storeCondFailures = sc_failures; }
844 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
845 unsigned size, unsigned flags)
849 Request *sreqLow = NULL;
850 Request *sreqHigh = NULL;
852 if (reqMade && translationStarted) {
854 sreqLow = savedSreqLow;
855 sreqHigh = savedSreqHigh;
857 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
858 thread->contextId(), threadNumber);
860 // Only split the request if the ISA supports unaligned accesses.
861 if (TheISA::HasUnalignedMemAcc) {
862 splitRequest(req, sreqLow, sreqHigh);
864 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
867 if (translationCompleted) {
868 if (fault == NoFault) {
869 effAddr = req->getVaddr();
872 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
874 // Commit will have to clean up whatever happened. Set this
875 // instruction as executed.
879 if (fault != NoFault) {
880 // Return a fixed value to keep simulation deterministic even
881 // along misspeculated paths.
888 traceData->setAddr(addr);
896 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
897 Addr addr, unsigned flags, uint64_t *res)
900 traceData->setAddr(addr);
905 Request *sreqLow = NULL;
906 Request *sreqHigh = NULL;
908 if (reqMade && translationStarted) {
910 sreqLow = savedSreqLow;
911 sreqHigh = savedSreqHigh;
913 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
914 thread->contextId(), threadNumber);
916 // Only split the request if the ISA supports unaligned accesses.
917 if (TheISA::HasUnalignedMemAcc) {
918 splitRequest(req, sreqLow, sreqHigh);
920 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
923 if (fault == NoFault && translationCompleted) {
924 effAddr = req->getVaddr();
927 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
935 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
936 RequestPtr &sreqHigh)
938 // Check to see if the request crosses the next level block boundary.
939 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
940 Addr addr = req->getVaddr();
941 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
942 assert(split_addr <= addr || split_addr - addr < block_size);
945 if (split_addr > addr) {
946 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
952 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
953 RequestPtr sreqHigh, uint64_t *res,
956 translationStarted = true;
958 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
959 WholeTranslationState *state =
960 new WholeTranslationState(req, NULL, res, mode);
962 // One translation if the request isn't split.
963 DataTranslation<BaseDynInst<Impl> > *trans =
964 new DataTranslation<BaseDynInst<Impl> >(this, state);
965 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
966 if (!translationCompleted) {
967 // Save memory requests.
968 savedReq = state->mainReq;
969 savedSreqLow = state->sreqLow;
970 savedSreqHigh = state->sreqHigh;
973 WholeTranslationState *state =
974 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
976 // Two translations when the request is split.
977 DataTranslation<BaseDynInst<Impl> > *stransLow =
978 new DataTranslation<BaseDynInst<Impl> >(this, state, 0);
979 DataTranslation<BaseDynInst<Impl> > *stransHigh =
980 new DataTranslation<BaseDynInst<Impl> >(this, state, 1);
982 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
983 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
984 if (!translationCompleted) {
985 // Save memory requests.
986 savedReq = state->mainReq;
987 savedSreqLow = state->sreqLow;
988 savedSreqHigh = state->sreqHigh;
995 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
997 fault = state->getFault();
999 if (state->isUncacheable())
1000 isUncacheable = true;
1002 if (fault == NoFault) {
1003 physEffAddr = state->getPaddr();
1004 memReqFlags = state->getFlags();
1006 if (state->mainReq->isCondSwap()) {
1008 state->mainReq->setExtraData(*state->res);
1012 state->deleteReqs();
1016 translationCompleted = true;
1019 #endif // __CPU_BASE_DYN_INST_HH__