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46 #ifndef __CPU_BASE_DYN_INST_HH__
47 #define __CPU_BASE_DYN_INST_HH__
55 #include "arch/generic/tlb.hh"
56 #include "arch/utility.hh"
57 #include "base/trace.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/checker/cpu.hh"
60 #include "cpu/exec_context.hh"
61 #include "cpu/exetrace.hh"
62 #include "cpu/inst_res.hh"
63 #include "cpu/inst_seq.hh"
64 #include "cpu/op_class.hh"
65 #include "cpu/static_inst.hh"
66 #include "cpu/translation.hh"
67 #include "mem/packet.hh"
68 #include "mem/request.hh"
69 #include "sim/byteswap.hh"
70 #include "sim/system.hh"
74 * Defines a dynamic instruction context.
78 class BaseDynInst : public ExecContext, public RefCounted
81 // Typedef for the CPU.
82 typedef typename Impl::CPUType ImplCPU;
83 typedef typename ImplCPU::ImplState ImplState;
84 using VecRegContainer = TheISA::VecRegContainer;
86 using LSQRequestPtr = typename Impl::CPUPol::LSQ::LSQRequest*;
87 using LQIterator = typename Impl::CPUPol::LSQUnit::LQIterator;
88 using SQIterator = typename Impl::CPUPol::LSQUnit::SQIterator;
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
104 IqEntry, /// Instruction is in the IQ
105 RobEntry, /// Instruction is in the ROB
106 LsqEntry, /// Instruction is in the LSQ
107 Completed, /// Instruction has completed
108 ResultReady, /// Instruction has its result
109 CanIssue, /// Instruction can issue and execute
110 Issued, /// Instruction has issued
111 Executed, /// Instruction has executed
112 CanCommit, /// Instruction can commit
113 AtCommit, /// Instruction has reached commit
114 Committed, /// Instruction has committed
115 Squashed, /// Instruction is squashed
116 SquashedInIQ, /// Instruction is squashed in the IQ
117 SquashedInLSQ, /// Instruction is squashed in the LSQ
118 SquashedInROB, /// Instruction is squashed in the ROB
119 RecoverInst, /// Is a recover instruction
120 BlockingInst, /// Is a blocking instruction
121 ThreadsyncWait, /// Is a thread synchronization instruction
122 SerializeBefore, /// Needs to serialize on
123 /// instructions ahead of it
124 SerializeAfter, /// Needs to serialize instructions behind it
125 SerializeHandled, /// Serialization has been handled
132 TranslationCompleted,
133 PossibleLoadViolation,
146 /** The sequence number of the instruction. */
149 /** The StaticInst used by this BaseDynInst. */
150 const StaticInstPtr staticInst;
152 /** Pointer to the Impl's CPU object. */
155 BaseCPU *getCpuPtr() { return cpu; }
157 /** Pointer to the thread state. */
160 /** The kind of fault this instruction has generated. */
163 /** InstRecord that tracks this instructions. */
164 Trace::InstRecord *traceData;
167 /** The result of the instruction; assumes an instruction can have many
168 * destination registers.
170 std::queue<InstResult> instResult;
172 /** PC state for this instruction. */
175 /* An amalgamation of a lot of boolean values into one */
176 std::bitset<MaxFlags> instFlags;
178 /** The status of this BaseDynInst. Several bits can be set. */
179 std::bitset<NumStatus> status;
181 /** Whether or not the source register is ready.
182 * @todo: Not sure this should be here vs the derived class.
184 std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
187 /** The thread this instruction is from. */
188 ThreadID threadNumber;
190 /** Iterator pointing to this BaseDynInst in the list of all insts. */
193 ////////////////////// Branch Data ///////////////
194 /** Predicted PC state after this instruction. */
195 TheISA::PCState predPC;
197 /** The Macroop if one exists */
198 const StaticInstPtr macroop;
200 /** How many source registers are ready. */
204 /////////////////////// Load Store Data //////////////////////
205 /** The effective virtual address (lds & stores only). */
208 /** The effective physical address. */
211 /** The memory request flags (from translation). */
212 unsigned memReqFlags;
214 /** data address space ID, for loads & stores. */
217 /** The size of the request */
220 /** Pointer to the data for the memory access. */
223 /** Load queue index. */
227 /** Store queue index. */
232 /////////////////////// TLB Miss //////////////////////
234 * Saved memory request (needed when the DTB address translation is
235 * delayed due to a hw page table walk).
237 LSQRequestPtr savedReq;
239 /////////////////////// Checker //////////////////////
240 // Need a copy of main request pointer to verify on writes.
241 RequestPtr reqToVerify;
244 /** Flattened register index of the destination registers of this
247 std::array<RegId, TheISA::MaxInstDestRegs> _flatDestRegIdx;
249 /** Physical register index of the destination registers of this
252 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _destRegIdx;
254 /** Physical register index of the source registers of this
257 std::array<PhysRegIdPtr, TheISA::MaxInstSrcRegs> _srcRegIdx;
259 /** Physical register index of the previous producers of the
260 * architected destinations.
262 std::array<PhysRegIdPtr, TheISA::MaxInstDestRegs> _prevDestRegIdx;
266 /** Records changes to result? */
267 void recordResult(bool f) { instFlags[RecordResult] = f; }
269 /** Is the effective virtual address valid. */
270 bool effAddrValid() const { return instFlags[EffAddrValid]; }
271 void effAddrValid(bool b) { instFlags[EffAddrValid] = b; }
273 /** Whether or not the memory operation is done. */
274 bool memOpDone() const { return instFlags[MemOpDone]; }
275 void memOpDone(bool f) { instFlags[MemOpDone] = f; }
277 bool notAnInst() const { return instFlags[NotAnInst]; }
278 void setNotAnInst() { instFlags[NotAnInst] = true; }
281 ////////////////////////////////////////////
283 // INSTRUCTION EXECUTION
285 ////////////////////////////////////////////
287 void demapPage(Addr vaddr, uint64_t asn)
289 cpu->demapPage(vaddr, asn);
291 void demapInstPage(Addr vaddr, uint64_t asn)
293 cpu->demapPage(vaddr, asn);
295 void demapDataPage(Addr vaddr, uint64_t asn)
297 cpu->demapPage(vaddr, asn);
300 Fault initiateMemRead(Addr addr, unsigned size, Request::Flags flags);
302 Fault writeMem(uint8_t *data, unsigned size, Addr addr,
303 Request::Flags flags, uint64_t *res);
305 Fault initiateMemAMO(Addr addr, unsigned size, Request::Flags flags,
306 AtomicOpFunctor *amo_op);
308 /** True if the DTB address translation has started. */
309 bool translationStarted() const { return instFlags[TranslationStarted]; }
310 void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
312 /** True if the DTB address translation has completed. */
313 bool translationCompleted() const { return instFlags[TranslationCompleted]; }
314 void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
316 /** True if this address was found to match a previous load and they issued
317 * out of order. If that happend, then it's only a problem if an incoming
318 * snoop invalidate modifies the line, in which case we need to squash.
319 * If nothing modified the line the order doesn't matter.
321 bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
322 void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
324 /** True if the address hit a external snoop while sitting in the LSQ.
325 * If this is true and a older instruction sees it, this instruction must
328 bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
329 void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
332 * Returns true if the DTB address translation is being delayed due to a hw
335 bool isTranslationDelayed() const
337 return (translationStarted() && !translationCompleted());
345 /** Returns the physical register index of the i'th destination
348 PhysRegIdPtr renamedDestRegIdx(int idx) const
350 return _destRegIdx[idx];
353 /** Returns the physical register index of the i'th source register. */
354 PhysRegIdPtr renamedSrcRegIdx(int idx) const
356 assert(TheISA::MaxInstSrcRegs > idx);
357 return _srcRegIdx[idx];
360 /** Returns the flattened register index of the i'th destination
363 const RegId& flattenedDestRegIdx(int idx) const
365 return _flatDestRegIdx[idx];
368 /** Returns the physical register index of the previous physical register
369 * that remapped to the same logical register index.
371 PhysRegIdPtr prevDestRegIdx(int idx) const
373 return _prevDestRegIdx[idx];
376 /** Renames a destination register to a physical register. Also records
377 * the previous physical register that the logical register mapped to.
379 void renameDestReg(int idx,
380 PhysRegIdPtr renamed_dest,
381 PhysRegIdPtr previous_rename)
383 _destRegIdx[idx] = renamed_dest;
384 _prevDestRegIdx[idx] = previous_rename;
387 /** Renames a source logical register to the physical register which
388 * has/will produce that logical register's result.
389 * @todo: add in whether or not the source register is ready.
391 void renameSrcReg(int idx, PhysRegIdPtr renamed_src)
393 _srcRegIdx[idx] = renamed_src;
396 /** Flattens a destination architectural register index into a logical
399 void flattenDestReg(int idx, const RegId& flattened_dest)
401 _flatDestRegIdx[idx] = flattened_dest;
403 /** BaseDynInst constructor given a binary instruction.
404 * @param staticInst A StaticInstPtr to the underlying instruction.
405 * @param pc The PC state for the instruction.
406 * @param predPC The predicted next PC state for the instruction.
407 * @param seq_num The sequence number of the instruction.
408 * @param cpu Pointer to the instruction's CPU.
410 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop,
411 TheISA::PCState pc, TheISA::PCState predPC,
412 InstSeqNum seq_num, ImplCPU *cpu);
414 /** BaseDynInst constructor given a StaticInst pointer.
415 * @param _staticInst The StaticInst for this BaseDynInst.
417 BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr ¯oop);
419 /** BaseDynInst destructor. */
423 /** Function to initialize variables in the constructors. */
427 /** Dumps out contents of this BaseDynInst. */
430 /** Dumps out contents of this BaseDynInst into given string. */
431 void dump(std::string &outstring);
433 /** Read this CPU's ID. */
434 int cpuId() const { return cpu->cpuId(); }
436 /** Read this CPU's Socket ID. */
437 uint32_t socketId() const { return cpu->socketId(); }
439 /** Read this CPU's data requestor ID */
440 MasterID masterId() const { return cpu->dataMasterId(); }
442 /** Read this context's system-wide ID **/
443 ContextID contextId() const { return thread->contextId(); }
445 /** Returns the fault type. */
446 Fault getFault() const { return fault; }
447 /** TODO: This I added for the LSQRequest side to be able to modify the
448 * fault. There should be a better mechanism in place. */
449 Fault& getFault() { return fault; }
451 /** Checks whether or not this instruction has had its branch target
452 * calculated yet. For now it is not utilized and is hacked to be
454 * @todo: Actually use this instruction.
456 bool doneTargCalc() { return false; }
458 /** Set the predicted target of this current instruction. */
459 void setPredTarg(const TheISA::PCState &_predPC)
464 const TheISA::PCState &readPredTarg() { return predPC; }
466 /** Returns the predicted PC immediately after the branch. */
467 Addr predInstAddr() { return predPC.instAddr(); }
469 /** Returns the predicted PC two instructions after the branch */
470 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
472 /** Returns the predicted micro PC after the branch */
473 Addr predMicroPC() { return predPC.microPC(); }
475 /** Returns whether the instruction was predicted taken or not. */
478 return instFlags[PredTaken];
481 void setPredTaken(bool predicted_taken)
483 instFlags[PredTaken] = predicted_taken;
486 /** Returns whether the instruction mispredicted. */
489 TheISA::PCState tempPC = pc;
490 TheISA::advancePC(tempPC, staticInst);
491 return !(tempPC == predPC);
495 // Instruction types. Forward checks to StaticInst object.
497 bool isNop() const { return staticInst->isNop(); }
498 bool isMemRef() const { return staticInst->isMemRef(); }
499 bool isLoad() const { return staticInst->isLoad(); }
500 bool isStore() const { return staticInst->isStore(); }
501 bool isAtomic() const { return staticInst->isAtomic(); }
502 bool isStoreConditional() const
503 { return staticInst->isStoreConditional(); }
504 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
505 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
506 bool isInteger() const { return staticInst->isInteger(); }
507 bool isFloating() const { return staticInst->isFloating(); }
508 bool isVector() const { return staticInst->isVector(); }
509 bool isControl() const { return staticInst->isControl(); }
510 bool isCall() const { return staticInst->isCall(); }
511 bool isReturn() const { return staticInst->isReturn(); }
512 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
513 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
514 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
515 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
516 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
517 bool isThreadSync() const { return staticInst->isThreadSync(); }
518 bool isSerializing() const { return staticInst->isSerializing(); }
519 bool isSerializeBefore() const
520 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
521 bool isSerializeAfter() const
522 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
523 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
524 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
525 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
526 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
527 bool isQuiesce() const { return staticInst->isQuiesce(); }
528 bool isIprAccess() const { return staticInst->isIprAccess(); }
529 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
530 bool isSyscall() const { return staticInst->isSyscall(); }
531 bool isMacroop() const { return staticInst->isMacroop(); }
532 bool isMicroop() const { return staticInst->isMicroop(); }
533 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
534 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
535 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
536 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
538 /** Temporarily sets this instruction as a serialize before instruction. */
539 void setSerializeBefore() { status.set(SerializeBefore); }
541 /** Clears the serializeBefore part of this instruction. */
542 void clearSerializeBefore() { status.reset(SerializeBefore); }
544 /** Checks if this serializeBefore is only temporarily set. */
545 bool isTempSerializeBefore() { return status[SerializeBefore]; }
547 /** Temporarily sets this instruction as a serialize after instruction. */
548 void setSerializeAfter() { status.set(SerializeAfter); }
550 /** Clears the serializeAfter part of this instruction.*/
551 void clearSerializeAfter() { status.reset(SerializeAfter); }
553 /** Checks if this serializeAfter is only temporarily set. */
554 bool isTempSerializeAfter() { return status[SerializeAfter]; }
556 /** Sets the serialization part of this instruction as handled. */
557 void setSerializeHandled() { status.set(SerializeHandled); }
559 /** Checks if the serialization part of this instruction has been
560 * handled. This does not apply to the temporary serializing
561 * state; it only applies to this instruction's own permanent
564 bool isSerializeHandled() { return status[SerializeHandled]; }
566 /** Returns the opclass of this instruction. */
567 OpClass opClass() const { return staticInst->opClass(); }
569 /** Returns the branch target address. */
570 TheISA::PCState branchTarget() const
571 { return staticInst->branchTarget(pc); }
573 /** Returns the number of source registers. */
574 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
576 /** Returns the number of destination registers. */
577 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
579 // the following are used to track physical register usage
580 // for machines with separate int & FP reg files
581 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
582 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
583 int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
584 int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
585 int8_t numVecElemDestRegs() const
587 return staticInst->numVecElemDestRegs();
590 numVecPredDestRegs() const
592 return staticInst->numVecPredDestRegs();
595 /** Returns the logical register index of the i'th destination register. */
596 const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
598 /** Returns the logical register index of the i'th source register. */
599 const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
601 /** Return the size of the instResult queue. */
602 uint8_t resultSize() { return instResult.size(); }
604 /** Pops a result off the instResult queue.
605 * If the result stack is empty, return the default value.
607 InstResult popResult(InstResult dflt = InstResult())
609 if (!instResult.empty()) {
610 InstResult t = instResult.front();
617 /** Pushes a result onto the instResult queue. */
619 /** Scalar result. */
621 void setScalarResult(T&& t)
623 if (instFlags[RecordResult]) {
624 instResult.push(InstResult(std::forward<T>(t),
625 InstResult::ResultType::Scalar));
629 /** Full vector result. */
631 void setVecResult(T&& t)
633 if (instFlags[RecordResult]) {
634 instResult.push(InstResult(std::forward<T>(t),
635 InstResult::ResultType::VecReg));
639 /** Vector element result. */
641 void setVecElemResult(T&& t)
643 if (instFlags[RecordResult]) {
644 instResult.push(InstResult(std::forward<T>(t),
645 InstResult::ResultType::VecElem));
649 /** Predicate result. */
651 void setVecPredResult(T&& t)
653 if (instFlags[RecordResult]) {
654 instResult.push(InstResult(std::forward<T>(t),
655 InstResult::ResultType::VecPredReg));
660 /** Records an integer register being set to a value. */
661 void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
663 setScalarResult(val);
666 /** Records a CC register being set to a value. */
667 void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
669 setScalarResult(val);
672 /** Record a vector register being set to a value */
673 void setVecRegOperand(const StaticInst *si, int idx,
674 const VecRegContainer& val)
679 /** Records an fp register being set to an integer value. */
681 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
683 setScalarResult(val);
686 /** Record a vector register being set to a value */
687 void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
689 setVecElemResult(val);
692 /** Record a vector register being set to a value */
693 void setVecPredRegOperand(const StaticInst *si, int idx,
694 const VecPredRegContainer& val)
696 setVecPredResult(val);
699 /** Records that one of the source registers is ready. */
700 void markSrcRegReady();
702 /** Marks a specific register as ready. */
703 void markSrcRegReady(RegIndex src_idx);
705 /** Returns if a source register is ready. */
706 bool isReadySrcRegIdx(int idx) const
708 return this->_readySrcRegIdx[idx];
711 /** Sets this instruction as completed. */
712 void setCompleted() { status.set(Completed); }
714 /** Returns whether or not this instruction is completed. */
715 bool isCompleted() const { return status[Completed]; }
717 /** Marks the result as ready. */
718 void setResultReady() { status.set(ResultReady); }
720 /** Returns whether or not the result is ready. */
721 bool isResultReady() const { return status[ResultReady]; }
723 /** Sets this instruction as ready to issue. */
724 void setCanIssue() { status.set(CanIssue); }
726 /** Returns whether or not this instruction is ready to issue. */
727 bool readyToIssue() const { return status[CanIssue]; }
729 /** Clears this instruction being able to issue. */
730 void clearCanIssue() { status.reset(CanIssue); }
732 /** Sets this instruction as issued from the IQ. */
733 void setIssued() { status.set(Issued); }
735 /** Returns whether or not this instruction has issued. */
736 bool isIssued() const { return status[Issued]; }
738 /** Clears this instruction as being issued. */
739 void clearIssued() { status.reset(Issued); }
741 /** Sets this instruction as executed. */
742 void setExecuted() { status.set(Executed); }
744 /** Returns whether or not this instruction has executed. */
745 bool isExecuted() const { return status[Executed]; }
747 /** Sets this instruction as ready to commit. */
748 void setCanCommit() { status.set(CanCommit); }
750 /** Clears this instruction as being ready to commit. */
751 void clearCanCommit() { status.reset(CanCommit); }
753 /** Returns whether or not this instruction is ready to commit. */
754 bool readyToCommit() const { return status[CanCommit]; }
756 void setAtCommit() { status.set(AtCommit); }
758 bool isAtCommit() { return status[AtCommit]; }
760 /** Sets this instruction as committed. */
761 void setCommitted() { status.set(Committed); }
763 /** Returns whether or not this instruction is committed. */
764 bool isCommitted() const { return status[Committed]; }
766 /** Sets this instruction as squashed. */
767 void setSquashed() { status.set(Squashed); }
769 /** Returns whether or not this instruction is squashed. */
770 bool isSquashed() const { return status[Squashed]; }
772 //Instruction Queue Entry
773 //-----------------------
774 /** Sets this instruction as a entry the IQ. */
775 void setInIQ() { status.set(IqEntry); }
777 /** Sets this instruction as a entry the IQ. */
778 void clearInIQ() { status.reset(IqEntry); }
780 /** Returns whether or not this instruction has issued. */
781 bool isInIQ() const { return status[IqEntry]; }
783 /** Sets this instruction as squashed in the IQ. */
784 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
786 /** Returns whether or not this instruction is squashed in the IQ. */
787 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
790 //Load / Store Queue Functions
791 //-----------------------
792 /** Sets this instruction as a entry the LSQ. */
793 void setInLSQ() { status.set(LsqEntry); }
795 /** Sets this instruction as a entry the LSQ. */
796 void removeInLSQ() { status.reset(LsqEntry); }
798 /** Returns whether or not this instruction is in the LSQ. */
799 bool isInLSQ() const { return status[LsqEntry]; }
801 /** Sets this instruction as squashed in the LSQ. */
802 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
804 /** Returns whether or not this instruction is squashed in the LSQ. */
805 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
808 //Reorder Buffer Functions
809 //-----------------------
810 /** Sets this instruction as a entry the ROB. */
811 void setInROB() { status.set(RobEntry); }
813 /** Sets this instruction as a entry the ROB. */
814 void clearInROB() { status.reset(RobEntry); }
816 /** Returns whether or not this instruction is in the ROB. */
817 bool isInROB() const { return status[RobEntry]; }
819 /** Sets this instruction as squashed in the ROB. */
820 void setSquashedInROB() { status.set(SquashedInROB); }
822 /** Returns whether or not this instruction is squashed in the ROB. */
823 bool isSquashedInROB() const { return status[SquashedInROB]; }
825 /** Read the PC state of this instruction. */
826 TheISA::PCState pcState() const { return pc; }
828 /** Set the PC state of this instruction. */
829 void pcState(const TheISA::PCState &val) { pc = val; }
831 /** Read the PC of this instruction. */
832 Addr instAddr() const { return pc.instAddr(); }
834 /** Read the PC of the next instruction. */
835 Addr nextInstAddr() const { return pc.nextInstAddr(); }
837 /**Read the micro PC of this instruction. */
838 Addr microPC() const { return pc.microPC(); }
840 bool readPredicate() const
842 return instFlags[Predicate];
845 void setPredicate(bool val)
847 instFlags[Predicate] = val;
850 traceData->setPredicate(val);
854 /** Sets the ASID. */
855 void setASID(short addr_space_id) { asid = addr_space_id; }
856 short getASID() { return asid; }
858 /** Sets the thread id. */
859 void setTid(ThreadID tid) { threadNumber = tid; }
861 /** Sets the pointer to the thread state. */
862 void setThreadState(ImplState *state) { thread = state; }
864 /** Returns the thread context. */
865 ThreadContext *tcBase() { return thread->getTC(); }
868 /** Returns whether or not the eff. addr. source registers are ready. */
869 bool eaSrcsReady() const;
871 /** Is this instruction's memory access strictly ordered? */
872 bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
873 void strictlyOrdered(bool so) { instFlags[IsStrictlyOrdered] = so; }
875 /** Has this instruction generated a memory request. */
876 bool hasRequest() const { return instFlags[ReqMade]; }
877 /** Assert this instruction has generated a memory request. */
878 void setRequest() { instFlags[ReqMade] = true; }
880 /** Returns iterator to this instruction in the list of all insts. */
881 ListIt &getInstListIt() { return instListIt; }
883 /** Sets iterator for this instruction in the list of all insts. */
884 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
887 /** Returns the number of consecutive store conditional failures. */
888 unsigned int readStCondFailures() const
889 { return thread->storeCondFailures; }
891 /** Sets the number of consecutive store conditional failures. */
892 void setStCondFailures(unsigned int sc_failures)
893 { thread->storeCondFailures = sc_failures; }
896 // monitor/mwait funtions
897 void armMonitor(Addr address) { cpu->armMonitor(threadNumber, address); }
898 bool mwait(PacketPtr pkt) { return cpu->mwait(threadNumber, pkt); }
899 void mwaitAtomic(ThreadContext *tc)
900 { return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb); }
901 AddressMonitor *getAddrMonitor()
902 { return cpu->getCpuAddrMonitor(threadNumber); }
907 BaseDynInst<Impl>::initiateMemRead(Addr addr, unsigned size,
908 Request::Flags flags)
910 return cpu->pushRequest(
911 dynamic_cast<typename DynInstPtr::PtrType>(this),
912 /* ld */ true, nullptr, size, addr, flags, nullptr);
917 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr,
918 Request::Flags flags, uint64_t *res)
920 return cpu->pushRequest(
921 dynamic_cast<typename DynInstPtr::PtrType>(this),
922 /* st */ false, data, size, addr, flags, res);
927 BaseDynInst<Impl>::initiateMemAMO(Addr addr, unsigned size,
928 Request::Flags flags,
929 AtomicOpFunctor *amo_op)
931 // atomic memory instructions do not have data to be written to memory yet
932 // since the atomic operations will be executed directly in cache/memory.
933 // Therefore, its `data` field is nullptr.
934 // Atomic memory requests need to carry their `amo_op` fields to cache/
936 return cpu->pushRequest(
937 dynamic_cast<typename DynInstPtr::PtrType>(this),
938 /* atomic */ false, nullptr, size, addr, flags, nullptr, amo_op);
941 #endif // __CPU_BASE_DYN_INST_HH__