src/cpu/base_dyn_inst.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_BASE_DYN_INST_HH__
  32 #define __CPU_BASE_DYN_INST_HH__
  33
  34 #include <list>
  35 #include <string>
  36
  37 #include "arch/faults.hh"
  38 #include "base/fast_alloc.hh"
  39 #include "base/trace.hh"
  40 #include "config/full_system.hh"
  41 #include "cpu/exetrace.hh"
  42 #include "cpu/inst_seq.hh"
  43 #include "cpu/op_class.hh"
  44 #include "cpu/static_inst.hh"
  45 #include "mem/packet.hh"
  46 #include "sim/system.hh"
  47
  48 /**
  49  * @file
  50  * Defines a dynamic instruction context.
  51  */
  52
  53 // Forward declaration.
  54 class StaticInstPtr;
  55
  56 template <class Impl>
  57 class BaseDynInst : public FastAlloc, public RefCounted
  58 {
  59   public:
  60     // Typedef for the CPU.
  61     typedef typename Impl::FullCPU FullCPU;
  62     typedef typename FullCPU::ImplState ImplState;
  63
  64     // Binary machine instruction type.
  65     typedef TheISA::MachInst MachInst;
  66     // Extended machine instruction type
  67     typedef TheISA::ExtMachInst ExtMachInst;
  68     // Logical register index type.
  69     typedef TheISA::RegIndex RegIndex;
  70     // Integer register type.
  71     typedef TheISA::IntReg IntReg;
  72     // Floating point register type.
  73     typedef TheISA::FloatReg FloatReg;
  74
  75     // The DynInstPtr type.
  76     typedef typename Impl::DynInstPtr DynInstPtr;
  77
  78     // The list of instructions iterator type.
  79     typedef typename std::list<DynInstPtr>::iterator ListIt;
  80
  81     enum {
  82         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
  83         MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
  84     };
  85
  86     /** The StaticInst used by this BaseDynInst. */
  87     StaticInstPtr staticInst;
  88
  89     ////////////////////////////////////////////
  90     //
  91     // INSTRUCTION EXECUTION
  92     //
  93     ////////////////////////////////////////////
  94     /** InstRecord that tracks this instructions. */
  95     Trace::InstRecord *traceData;
  96
  97     /**
  98      * Does a read to a given address.
  99      * @param addr The address to read.
 100      * @param data The read's data is written into this parameter.
 101      * @param flags The request's flags.
 102      * @return Returns any fault due to the read.
 103      */
 104     template <class T>
 105     Fault read(Addr addr, T &data, unsigned flags);
 106
 107     /**
 108      * Does a write to a given address.
 109      * @param data The data to be written.
 110      * @param addr The address to write to.
 111      * @param flags The request's flags.
 112      * @param res The result of the write (for load locked/store conditionals).
 113      * @return Returns any fault due to the write.
 114      */
 115     template <class T>
 116     Fault write(T data, Addr addr, unsigned flags,
 117                         uint64_t *res);
 118
 119     void prefetch(Addr addr, unsigned flags);
 120     void writeHint(Addr addr, int size, unsigned flags);
 121     Fault copySrcTranslate(Addr src);
 122     Fault copy(Addr dest);
 123
 124     /** @todo: Consider making this private. */
 125   public:
 126     /** The sequence number of the instruction. */
 127     InstSeqNum seqNum;
 128
 129     /** Is the instruction in the IQ */
 130     bool iqEntry;
 131
 132     /** Is the instruction in the ROB */
 133     bool robEntry;
 134
 135     /** Is the instruction in the LSQ */
 136     bool lsqEntry;
 137
 138     /** Is the instruction completed. */
 139     bool completed;
 140
 141     /** Is the instruction's result ready. */
 142     bool resultReady;
 143
 144     /** Can this instruction issue. */
 145     bool canIssue;
 146
 147     /** Has this instruction issued. */
 148     bool issued;
 149
 150     /** Has this instruction executed (or made it through execute) yet. */
 151     bool executed;
 152
 153     /** Can this instruction commit. */
 154     bool canCommit;
 155
 156     /** Is this instruction committed. */
 157     bool committed;
 158
 159     /** Is this instruction squashed. */
 160     bool squashed;
 161
 162     /** Is this instruction squashed in the instruction queue. */
 163     bool squashedInIQ;
 164
 165     /** Is this instruction squashed in the instruction queue. */
 166     bool squashedInLSQ;
 167
 168     /** Is this instruction squashed in the instruction queue. */
 169     bool squashedInROB;
 170
 171     /** Is this a recover instruction. */
 172     bool recoverInst;
 173
 174     /** Is this a thread blocking instruction. */
 175     bool blockingInst;  /* this inst has called thread_block() */
 176
 177     /** Is this a thread syncrhonization instruction. */
 178     bool threadsyncWait;
 179
 180     /** The thread this instruction is from. */
 181     short threadNumber;
 182
 183     /** data address space ID, for loads & stores. */
 184     short asid;
 185
 186     /** How many source registers are ready. */
 187     unsigned readyRegs;
 188
 189     /** Pointer to the FullCPU object. */
 190     FullCPU *cpu;
 191
 192     /** Pointer to the thread state. */
 193     ImplState *thread;
 194
 195     /** The kind of fault this instruction has generated. */
 196     Fault fault;
 197
 198     /** The memory request. */
 199     Request *req;
 200
 201     /** Pointer to the data for the memory access. */
 202     uint8_t *memData;
 203
 204     /** The effective virtual address (lds & stores only). */
 205     Addr effAddr;
 206
 207     /** The effective physical address. */
 208     Addr physEffAddr;
 209
 210     /** Effective virtual address for a copy source. */
 211     Addr copySrcEffAddr;
 212
 213     /** Effective physical address for a copy source. */
 214     Addr copySrcPhysEffAddr;
 215
 216     /** The memory request flags (from translation). */
 217     unsigned memReqFlags;
 218
 219     /** The size of the data to be stored. */
 220     int storeSize;
 221
 222     /** The data to be stored. */
 223     IntReg storeData;
 224
 225     union Result {
 226         uint64_t integer;
 227         float fp;
 228         double dbl;
 229     };
 230
 231     /** The result of the instruction; assumes for now that there's only one
 232      *  destination register.
 233      */
 234     Result instResult;
 235
 236     /** PC of this instruction. */
 237     Addr PC;
 238
 239     /** Next non-speculative PC.  It is not filled in at fetch, but rather
 240      *  once the target of the branch is truly known (either decode or
 241      *  execute).
 242      */
 243     Addr nextPC;
 244
 245     /** Predicted next PC. */
 246     Addr predPC;
 247
 248     /** Count of total number of dynamic instructions. */
 249     static int instcount;
 250
 251 #ifdef DEBUG
 252     void dumpSNList();
 253 #endif
 254
 255     /** Whether or not the source register is ready.
 256      *  @todo: Not sure this should be here vs the derived class.
 257      */
 258     bool _readySrcRegIdx[MaxInstSrcRegs];
 259
 260   public:
 261     /** BaseDynInst constructor given a binary instruction.
 262      *  @param inst The binary instruction.
 263      *  @param PC The PC of the instruction.
 264      *  @param pred_PC The predicted next PC.
 265      *  @param seq_num The sequence number of the instruction.
 266      *  @param cpu Pointer to the instruction's CPU.
 267      */
 268     BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
 269                 FullCPU *cpu);
 270
 271     /** BaseDynInst constructor given a StaticInst pointer.
 272      *  @param _staticInst The StaticInst for this BaseDynInst.
 273      */
 274     BaseDynInst(StaticInstPtr &_staticInst);
 275
 276     /** BaseDynInst destructor. */
 277     ~BaseDynInst();
 278
 279   private:
 280     /** Function to initialize variables in the constructors. */
 281     void initVars();
 282
 283   public:
 284     /** Dumps out contents of this BaseDynInst. */
 285     void dump();
 286
 287     /** Dumps out contents of this BaseDynInst into given string. */
 288     void dump(std::string &outstring);
 289
 290     /** Returns the fault type. */
 291     Fault getFault() { return fault; }
 292
 293     /** Checks whether or not this instruction has had its branch target
 294      *  calculated yet.  For now it is not utilized and is hacked to be
 295      *  always false.
 296      *  @todo: Actually use this instruction.
 297      */
 298     bool doneTargCalc() { return false; }
 299
 300     /** Returns the next PC.  This could be the speculative next PC if it is
 301      *  called prior to the actual branch target being calculated.
 302      */
 303     Addr readNextPC() { return nextPC; }
 304
 305     /** Set the predicted target of this current instruction. */
 306     void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
 307
 308     /** Returns the predicted target of the branch. */
 309     Addr readPredTarg() { return predPC; }
 310
 311     /** Returns whether the instruction was predicted taken or not. */
 312     bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
 313
 314     /** Returns whether the instruction mispredicted. */
 315     bool mispredicted() { return predPC != nextPC; }
 316
 317     //
 318     //  Instruction types.  Forward checks to StaticInst object.
 319     //
 320     bool isNop()          const { return staticInst->isNop(); }
 321     bool isMemRef()       const { return staticInst->isMemRef(); }
 322     bool isLoad()         const { return staticInst->isLoad(); }
 323     bool isStore()        const { return staticInst->isStore(); }
 324     bool isStoreConditional() const
 325     { return staticInst->isStoreConditional(); }
 326     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
 327     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
 328     bool isCopy()         const { return staticInst->isCopy(); }
 329     bool isInteger()      const { return staticInst->isInteger(); }
 330     bool isFloating()     const { return staticInst->isFloating(); }
 331     bool isControl()      const { return staticInst->isControl(); }
 332     bool isCall()         const { return staticInst->isCall(); }
 333     bool isReturn()       const { return staticInst->isReturn(); }
 334     bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
 335     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
 336     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
 337     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
 338     bool isThreadSync()   const { return staticInst->isThreadSync(); }
 339     bool isSerializing()  const { return staticInst->isSerializing(); }
 340     bool isSerializeBefore() const
 341     { return staticInst->isSerializeBefore() || serializeBefore; }
 342     bool isSerializeAfter() const
 343     { return staticInst->isSerializeAfter() || serializeAfter; }
 344     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
 345     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
 346     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
 347     bool isQuiesce() const { return staticInst->isQuiesce(); }
 348     bool isIprAccess() const { return staticInst->isIprAccess(); }
 349     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
 350
 351     /** Temporarily sets this instruction as a serialize before instruction. */
 352     void setSerializeBefore() { serializeBefore = true; }
 353
 354     /** Clears the serializeBefore part of this instruction. */
 355     void clearSerializeBefore() { serializeBefore = false; }
 356
 357     /** Checks if this serializeBefore is only temporarily set. */
 358     bool isTempSerializeBefore() { return serializeBefore; }
 359
 360     /** Tracks if instruction has been externally set as serializeBefore. */
 361     bool serializeBefore;
 362
 363     /** Temporarily sets this instruction as a serialize after instruction. */
 364     void setSerializeAfter() { serializeAfter = true; }
 365
 366     /** Clears the serializeAfter part of this instruction.*/
 367     void clearSerializeAfter() { serializeAfter = false; }
 368
 369     /** Checks if this serializeAfter is only temporarily set. */
 370     bool isTempSerializeAfter() { return serializeAfter; }
 371
 372     /** Tracks if instruction has been externally set as serializeAfter. */
 373     bool serializeAfter;
 374
 375     /** Checks if the serialization part of this instruction has been
 376      *  handled.  This does not apply to the temporary serializing
 377      *  state; it only applies to this instruction's own permanent
 378      *  serializing state.
 379      */
 380     bool isSerializeHandled() { return serializeHandled; }
 381
 382     /** Sets the serialization part of this instruction as handled. */
 383     void setSerializeHandled() { serializeHandled = true; }
 384
 385     /** Whether or not the serialization of this instruction has been handled. */
 386     bool serializeHandled;
 387
 388     /** Returns the opclass of this instruction. */
 389     OpClass opClass() const { return staticInst->opClass(); }
 390
 391     /** Returns the branch target address. */
 392     Addr branchTarget() const { return staticInst->branchTarget(PC); }
 393
 394     /** Returns the number of source registers. */
 395     int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
 396
 397     /** Returns the number of destination registers. */
 398     int8_t numDestRegs() const { return staticInst->numDestRegs(); }
 399
 400     // the following are used to track physical register usage
 401     // for machines with separate int & FP reg files
 402     int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
 403     int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
 404
 405     /** Returns the logical register index of the i'th destination register. */
 406     RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
 407
 408     /** Returns the logical register index of the i'th source register. */
 409     RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
 410
 411     /** Returns the result of an integer instruction. */
 412     uint64_t readIntResult() { return instResult.integer; }
 413
 414     /** Returns the result of a floating point instruction. */
 415     float readFloatResult() { return instResult.fp; }
 416
 417     /** Returns the result of a floating point (double) instruction. */
 418     double readDoubleResult() { return instResult.dbl; }
 419
 420     /** Records an integer register being set to a value. */
 421     void setIntReg(const StaticInst *si, int idx, uint64_t val)
 422     {
 423         instResult.integer = val;
 424     }
 425
 426     /** Records an fp register being set to a value. */
 427     void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
 428     {
 429         if (width == 32)
 430             instResult.fp = val;
 431         else if (width == 64)
 432             instResult.dbl = val;
 433         else
 434             panic("Unsupported width!");
 435     }
 436
 437     /** Records an fp register being set to a value. */
 438     void setFloatReg(const StaticInst *si, int idx, FloatReg val)
 439     {
 440         instResult.fp = val;
 441     }
 442
 443     /** Records an fp register being set to an integer value. */
 444     void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
 445     {
 446         instResult.integer = val;
 447     }
 448
 449     /** Records an fp register being set to an integer value. */
 450     void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
 451     {
 452         instResult.integer = val;
 453     }
 454
 455     /** Records that one of the source registers is ready. */
 456     void markSrcRegReady();
 457
 458     /** Marks a specific register as ready. */
 459     void markSrcRegReady(RegIndex src_idx);
 460
 461     /** Returns if a source register is ready. */
 462     bool isReadySrcRegIdx(int idx) const
 463     {
 464         return this->_readySrcRegIdx[idx];
 465     }
 466
 467     /** Sets this instruction as completed. */
 468     void setCompleted() { completed = true; }
 469
 470     /** Returns whether or not this instruction is completed. */
 471     bool isCompleted() const { return completed; }
 472
 473     void setResultReady() { resultReady = true; }
 474
 475     bool isResultReady() const { return resultReady; }
 476
 477     /** Sets this instruction as ready to issue. */
 478     void setCanIssue() { canIssue = true; }
 479
 480     /** Returns whether or not this instruction is ready to issue. */
 481     bool readyToIssue() const { return canIssue; }
 482
 483     /** Sets this instruction as issued from the IQ. */
 484     void setIssued() { issued = true; }
 485
 486     /** Returns whether or not this instruction has issued. */
 487     bool isIssued() const { return issued; }
 488
 489     /** Sets this instruction as executed. */
 490     void setExecuted() { executed = true; }
 491
 492     /** Returns whether or not this instruction has executed. */
 493     bool isExecuted() const { return executed; }
 494
 495     /** Sets this instruction as ready to commit. */
 496     void setCanCommit() { canCommit = true; }
 497
 498     /** Clears this instruction as being ready to commit. */
 499     void clearCanCommit() { canCommit = false; }
 500
 501     /** Returns whether or not this instruction is ready to commit. */
 502     bool readyToCommit() const { return canCommit; }
 503
 504     /** Sets this instruction as committed. */
 505     void setCommitted() { committed = true; }
 506
 507     /** Returns whether or not this instruction is committed. */
 508     bool isCommitted() const { return committed; }
 509
 510     /** Sets this instruction as squashed. */
 511     void setSquashed() { squashed = true; }
 512
 513     /** Returns whether or not this instruction is squashed. */
 514     bool isSquashed() const { return squashed; }
 515
 516     //Instruction Queue Entry
 517     //-----------------------
 518     /** Sets this instruction as a entry the IQ. */
 519     void setInIQ() { iqEntry = true; }
 520
 521     /** Sets this instruction as a entry the IQ. */
 522     void removeInIQ() { iqEntry = false; }
 523
 524     /** Sets this instruction as squashed in the IQ. */
 525     void setSquashedInIQ() { squashedInIQ = true; squashed = true;}
 526
 527     /** Returns whether or not this instruction is squashed in the IQ. */
 528     bool isSquashedInIQ() const { return squashedInIQ; }
 529
 530     /** Returns whether or not this instruction has issued. */
 531     bool isInIQ() const { return iqEntry; }
 532
 533
 534     //Load / Store Queue Functions
 535     //-----------------------
 536     /** Sets this instruction as a entry the LSQ. */
 537     void setInLSQ() { lsqEntry = true; }
 538
 539     /** Sets this instruction as a entry the LSQ. */
 540     void removeInLSQ() { lsqEntry = false; }
 541
 542     /** Sets this instruction as squashed in the LSQ. */
 543     void setSquashedInLSQ() { squashedInLSQ = true;}
 544
 545     /** Returns whether or not this instruction is squashed in the LSQ. */
 546     bool isSquashedInLSQ() const { return squashedInLSQ; }
 547
 548     /** Returns whether or not this instruction is in the LSQ. */
 549     bool isInLSQ() const { return lsqEntry; }
 550
 551
 552     //Reorder Buffer Functions
 553     //-----------------------
 554     /** Sets this instruction as a entry the ROB. */
 555     void setInROB() { robEntry = true; }
 556
 557     /** Sets this instruction as a entry the ROB. */
 558     void removeInROB() { robEntry = false; }
 559
 560     /** Sets this instruction as squashed in the ROB. */
 561     void setSquashedInROB() { squashedInROB = true; }
 562
 563     /** Returns whether or not this instruction is squashed in the ROB. */
 564     bool isSquashedInROB() const { return squashedInROB; }
 565
 566     /** Returns whether or not this instruction is in the ROB. */
 567     bool isInROB() const { return robEntry; }
 568
 569     /** Read the PC of this instruction. */
 570     const Addr readPC() const { return PC; }
 571
 572     /** Set the next PC of this instruction (its actual target). */
 573     void setNextPC(uint64_t val)
 574     {
 575         nextPC = val;
 576     }
 577
 578     /** Sets the ASID. */
 579     void setASID(short addr_space_id) { asid = addr_space_id; }
 580
 581     /** Sets the thread id. */
 582     void setTid(unsigned tid) { threadNumber = tid; }
 583
 584     void setThreadState(ImplState *state) { thread = state; }
 585
 586     /** Returns the thread context.
 587      */
 588     ThreadContext *tcBase() { return thread->getTC(); }
 589
 590   private:
 591     /** Instruction effective address.
 592      *  @todo: Consider if this is necessary or not.
 593      */
 594     Addr instEffAddr;
 595
 596     /** Whether or not the effective address calculation is completed.
 597      *  @todo: Consider if this is necessary or not.
 598      */
 599     bool eaCalcDone;
 600
 601   public:
 602     /** Sets the effective address. */
 603     void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
 604
 605     /** Returns the effective address. */
 606     const Addr &getEA() const { return instEffAddr; }
 607
 608     /** Returns whether or not the eff. addr. calculation has been completed. */
 609     bool doneEACalc() { return eaCalcDone; }
 610
 611     /** Returns whether or not the eff. addr. source registers are ready. */
 612     bool eaSrcsReady();
 613
 614     /** Whether or not the memory operation is done. */
 615     bool memOpDone;
 616
 617   public:
 618     /** Load queue index. */
 619     int16_t lqIdx;
 620
 621     /** Store queue index. */
 622     int16_t sqIdx;
 623
 624     bool reachedCommit;
 625
 626     /** Iterator pointing to this BaseDynInst in the list of all insts. */
 627     ListIt instListIt;
 628
 629     /** Returns iterator to this instruction in the list of all insts. */
 630     ListIt &getInstListIt() { return instListIt; }
 631
 632     /** Sets iterator for this instruction in the list of all insts. */
 633     void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
 634 };
 635
 636 template<class Impl>
 637 template<class T>
 638 inline Fault
 639 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
 640 {
 641     // Sometimes reads will get retried, so they may come through here
 642     // twice.
 643     if (!req) {
 644         req = new Request();
 645         req->setVirt(asid, addr, sizeof(T), flags, this->PC);
 646         req->setThreadContext(thread->readCpuId(), threadNumber);
 647     } else {
 648         assert(addr == req->getVaddr());
 649     }
 650
 651     if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
 652         TheISA::VMPageSize) {
 653         return TheISA::genAlignmentFault();
 654     }
 655
 656     fault = cpu->translateDataReadReq(req, thread);
 657
 658     if (fault == NoFault) {
 659         effAddr = req->getVaddr();
 660         physEffAddr = req->getPaddr();
 661         memReqFlags = req->getFlags();
 662
 663 #if 0
 664         if (cpu->system->memctrl->badaddr(physEffAddr)) {
 665             fault = TheISA::genMachineCheckFault();
 666             data = (T)-1;
 667             this->setExecuted();
 668         } else {
 669             fault = cpu->read(req, data, lqIdx);
 670         }
 671 #else
 672         fault = cpu->read(req, data, lqIdx);
 673 #endif
 674     } else {
 675         // Return a fixed value to keep simulation deterministic even
 676         // along misspeculated paths.
 677         data = (T)-1;
 678
 679         // Commit will have to clean up whatever happened.  Set this
 680         // instruction as executed.
 681         this->setExecuted();
 682     }
 683
 684     if (traceData) {
 685         traceData->setAddr(addr);
 686         traceData->setData(data);
 687     }
 688
 689     return fault;
 690 }
 691
 692 template<class Impl>
 693 template<class T>
 694 inline Fault
 695 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 696 {
 697     if (traceData) {
 698         traceData->setAddr(addr);
 699         traceData->setData(data);
 700     }
 701
 702     assert(req == NULL);
 703
 704     req = new Request();
 705     req->setVirt(asid, addr, sizeof(T), flags, this->PC);
 706     req->setThreadContext(thread->readCpuId(), threadNumber);
 707
 708     if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
 709         TheISA::VMPageSize) {
 710         return TheISA::genAlignmentFault();
 711     }
 712
 713     fault = cpu->translateDataWriteReq(req, thread);
 714
 715     if (fault == NoFault) {
 716         effAddr = req->getVaddr();
 717         physEffAddr = req->getPaddr();
 718         memReqFlags = req->getFlags();
 719 #if 0
 720         if (cpu->system->memctrl->badaddr(physEffAddr)) {
 721             fault = TheISA::genMachineCheckFault();
 722         } else {
 723             fault = cpu->write(req, data, sqIdx);
 724         }
 725 #else
 726         fault = cpu->write(req, data, sqIdx);
 727 #endif
 728     }
 729
 730     if (res) {
 731         // always return some result to keep misspeculated paths
 732         // (which will ignore faults) deterministic
 733         *res = (fault == NoFault) ? req->getScResult() : 0;
 734     }
 735
 736     return fault;
 737 }
 738
 739 #endif // __CPU_BASE_DYN_INST_HH__