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31 #ifndef __CPU_BASE_DYN_INST_HH__
32 #define __CPU_BASE_DYN_INST_HH__
38 #include "arch/faults.hh"
39 #include "base/fast_alloc.hh"
40 #include "base/trace.hh"
41 #include "config/full_system.hh"
42 #include "cpu/exetrace.hh"
43 #include "cpu/inst_seq.hh"
44 #include "cpu/op_class.hh"
45 #include "cpu/static_inst.hh"
46 #include "mem/packet.hh"
47 #include "sim/system.hh"
51 * Defines a dynamic instruction context.
54 // Forward declaration.
58 class BaseDynInst : public FastAlloc, public RefCounted
61 // Typedef for the CPU.
62 typedef typename Impl::CPUType ImplCPU;
63 typedef typename ImplCPU::ImplState ImplState;
65 // Binary machine instruction type.
66 typedef TheISA::MachInst MachInst;
67 // Extended machine instruction type
68 typedef TheISA::ExtMachInst ExtMachInst;
69 // Logical register index type.
70 typedef TheISA::RegIndex RegIndex;
71 // Integer register type.
72 typedef TheISA::IntReg IntReg;
73 // Floating point register type.
74 typedef TheISA::FloatReg FloatReg;
76 // The DynInstPtr type.
77 typedef typename Impl::DynInstPtr DynInstPtr;
79 // The list of instructions iterator type.
80 typedef typename std::list<DynInstPtr>::iterator ListIt;
83 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
84 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
87 /** The StaticInst used by this BaseDynInst. */
88 StaticInstPtr staticInst;
90 ////////////////////////////////////////////
92 // INSTRUCTION EXECUTION
94 ////////////////////////////////////////////
95 /** InstRecord that tracks this instructions. */
96 Trace::InstRecord *traceData;
99 * Does a read to a given address.
100 * @param addr The address to read.
101 * @param data The read's data is written into this parameter.
102 * @param flags The request's flags.
103 * @return Returns any fault due to the read.
106 Fault read(Addr addr, T &data, unsigned flags);
109 * Does a write to a given address.
110 * @param data The data to be written.
111 * @param addr The address to write to.
112 * @param flags The request's flags.
113 * @param res The result of the write (for load locked/store conditionals).
114 * @return Returns any fault due to the write.
117 Fault write(T data, Addr addr, unsigned flags,
120 void prefetch(Addr addr, unsigned flags);
121 void writeHint(Addr addr, int size, unsigned flags);
122 Fault copySrcTranslate(Addr src);
123 Fault copy(Addr dest);
125 /** @todo: Consider making this private. */
127 /** The sequence number of the instruction. */
131 IqEntry, /// Instruction is in the IQ
132 RobEntry, /// Instruction is in the ROB
133 LsqEntry, /// Instruction is in the LSQ
134 Completed, /// Instruction has completed
135 ResultReady, /// Instruction has its result
136 CanIssue, /// Instruction can issue and execute
137 Issued, /// Instruction has issued
138 Executed, /// Instruction has executed
139 CanCommit, /// Instruction can commit
140 AtCommit, /// Instruction has reached commit
141 Committed, /// Instruction has committed
142 Squashed, /// Instruction is squashed
143 SquashedInIQ, /// Instruction is squashed in the IQ
144 SquashedInLSQ, /// Instruction is squashed in the LSQ
145 SquashedInROB, /// Instruction is squashed in the ROB
146 RecoverInst, /// Is a recover instruction
147 BlockingInst, /// Is a blocking instruction
148 ThreadsyncWait, /// Is a thread synchronization instruction
149 SerializeBefore, /// Needs to serialize on
150 /// instructions ahead of it
151 SerializeAfter, /// Needs to serialize instructions behind it
152 SerializeHandled, /// Serialization has been handled
156 /** The status of this BaseDynInst. Several bits can be set. */
157 std::bitset<NumStatus> status;
159 /** The thread this instruction is from. */
162 /** data address space ID, for loads & stores. */
165 /** How many source registers are ready. */
168 /** Pointer to the Impl's CPU object. */
171 /** Pointer to the thread state. */
174 /** The kind of fault this instruction has generated. */
177 /** The memory request. */
180 /** Pointer to the data for the memory access. */
183 /** The effective virtual address (lds & stores only). */
186 /** The effective physical address. */
189 /** Effective virtual address for a copy source. */
192 /** Effective physical address for a copy source. */
193 Addr copySrcPhysEffAddr;
195 /** The memory request flags (from translation). */
196 unsigned memReqFlags;
204 /** The result of the instruction; assumes for now that there's only one
205 * destination register.
209 /** PC of this instruction. */
212 /** Next non-speculative PC. It is not filled in at fetch, but rather
213 * once the target of the branch is truly known (either decode or
218 /** Predicted next PC. */
221 /** Count of total number of dynamic instructions. */
222 static int instcount;
228 /** Whether or not the source register is ready.
229 * @todo: Not sure this should be here vs the derived class.
231 bool _readySrcRegIdx[MaxInstSrcRegs];
234 /** BaseDynInst constructor given a binary instruction.
235 * @param inst The binary instruction.
236 * @param PC The PC of the instruction.
237 * @param pred_PC The predicted next PC.
238 * @param seq_num The sequence number of the instruction.
239 * @param cpu Pointer to the instruction's CPU.
241 BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num,
244 /** BaseDynInst constructor given a StaticInst pointer.
245 * @param _staticInst The StaticInst for this BaseDynInst.
247 BaseDynInst(StaticInstPtr &_staticInst);
249 /** BaseDynInst destructor. */
253 /** Function to initialize variables in the constructors. */
257 /** Dumps out contents of this BaseDynInst. */
260 /** Dumps out contents of this BaseDynInst into given string. */
261 void dump(std::string &outstring);
263 /** Returns the fault type. */
264 Fault getFault() { return fault; }
266 /** Checks whether or not this instruction has had its branch target
267 * calculated yet. For now it is not utilized and is hacked to be
269 * @todo: Actually use this instruction.
271 bool doneTargCalc() { return false; }
273 /** Returns the next PC. This could be the speculative next PC if it is
274 * called prior to the actual branch target being calculated.
276 Addr readNextPC() { return nextPC; }
278 /** Set the predicted target of this current instruction. */
279 void setPredTarg(Addr predicted_PC) { predPC = predicted_PC; }
281 /** Returns the predicted target of the branch. */
282 Addr readPredTarg() { return predPC; }
284 /** Returns whether the instruction was predicted taken or not. */
285 bool predTaken() { return predPC != (PC + sizeof(MachInst)); }
287 /** Returns whether the instruction mispredicted. */
288 bool mispredicted() { return predPC != nextPC; }
291 // Instruction types. Forward checks to StaticInst object.
293 bool isNop() const { return staticInst->isNop(); }
294 bool isMemRef() const { return staticInst->isMemRef(); }
295 bool isLoad() const { return staticInst->isLoad(); }
296 bool isStore() const { return staticInst->isStore(); }
297 bool isStoreConditional() const
298 { return staticInst->isStoreConditional(); }
299 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
300 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
301 bool isCopy() const { return staticInst->isCopy(); }
302 bool isInteger() const { return staticInst->isInteger(); }
303 bool isFloating() const { return staticInst->isFloating(); }
304 bool isControl() const { return staticInst->isControl(); }
305 bool isCall() const { return staticInst->isCall(); }
306 bool isReturn() const { return staticInst->isReturn(); }
307 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
308 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
309 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
310 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
311 bool isThreadSync() const { return staticInst->isThreadSync(); }
312 bool isSerializing() const { return staticInst->isSerializing(); }
313 bool isSerializeBefore() const
314 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
315 bool isSerializeAfter() const
316 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
317 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
318 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
319 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
320 bool isQuiesce() const { return staticInst->isQuiesce(); }
321 bool isIprAccess() const { return staticInst->isIprAccess(); }
322 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
324 /** Temporarily sets this instruction as a serialize before instruction. */
325 void setSerializeBefore() { status.set(SerializeBefore); }
327 /** Clears the serializeBefore part of this instruction. */
328 void clearSerializeBefore() { status.reset(SerializeBefore); }
330 /** Checks if this serializeBefore is only temporarily set. */
331 bool isTempSerializeBefore() { return status[SerializeBefore]; }
333 /** Temporarily sets this instruction as a serialize after instruction. */
334 void setSerializeAfter() { status.set(SerializeAfter); }
336 /** Clears the serializeAfter part of this instruction.*/
337 void clearSerializeAfter() { status.reset(SerializeAfter); }
339 /** Checks if this serializeAfter is only temporarily set. */
340 bool isTempSerializeAfter() { return status[SerializeAfter]; }
342 /** Sets the serialization part of this instruction as handled. */
343 void setSerializeHandled() { status.set(SerializeHandled); }
345 /** Checks if the serialization part of this instruction has been
346 * handled. This does not apply to the temporary serializing
347 * state; it only applies to this instruction's own permanent
350 bool isSerializeHandled() { return status[SerializeHandled]; }
352 /** Returns the opclass of this instruction. */
353 OpClass opClass() const { return staticInst->opClass(); }
355 /** Returns the branch target address. */
356 Addr branchTarget() const { return staticInst->branchTarget(PC); }
358 /** Returns the number of source registers. */
359 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
361 /** Returns the number of destination registers. */
362 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
364 // the following are used to track physical register usage
365 // for machines with separate int & FP reg files
366 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
367 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
369 /** Returns the logical register index of the i'th destination register. */
370 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
372 /** Returns the logical register index of the i'th source register. */
373 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
375 /** Returns the result of an integer instruction. */
376 uint64_t readIntResult() { return instResult.integer; }
378 /** Returns the result of a floating point instruction. */
379 float readFloatResult() { return instResult.fp; }
381 /** Returns the result of a floating point (double) instruction. */
382 double readDoubleResult() { return instResult.dbl; }
384 /** Records an integer register being set to a value. */
385 void setIntReg(const StaticInst *si, int idx, uint64_t val)
387 instResult.integer = val;
390 /** Records an fp register being set to a value. */
391 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
395 else if (width == 64)
396 instResult.dbl = val;
398 panic("Unsupported width!");
401 /** Records an fp register being set to a value. */
402 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
407 /** Records an fp register being set to an integer value. */
408 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
410 instResult.integer = val;
413 /** Records an fp register being set to an integer value. */
414 void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
416 instResult.integer = val;
419 /** Records that one of the source registers is ready. */
420 void markSrcRegReady();
422 /** Marks a specific register as ready. */
423 void markSrcRegReady(RegIndex src_idx);
425 /** Returns if a source register is ready. */
426 bool isReadySrcRegIdx(int idx) const
428 return this->_readySrcRegIdx[idx];
431 /** Sets this instruction as completed. */
432 void setCompleted() { status.set(Completed); }
434 /** Returns whether or not this instruction is completed. */
435 bool isCompleted() const { return status[Completed]; }
437 /** Marks the result as ready. */
438 void setResultReady() { status.set(ResultReady); }
440 /** Returns whether or not the result is ready. */
441 bool isResultReady() const { return status[ResultReady]; }
443 /** Sets this instruction as ready to issue. */
444 void setCanIssue() { status.set(CanIssue); }
446 /** Returns whether or not this instruction is ready to issue. */
447 bool readyToIssue() const { return status[CanIssue]; }
449 /** Sets this instruction as issued from the IQ. */
450 void setIssued() { status.set(Issued); }
452 /** Returns whether or not this instruction has issued. */
453 bool isIssued() const { return status[Issued]; }
455 /** Sets this instruction as executed. */
456 void setExecuted() { status.set(Executed); }
458 /** Returns whether or not this instruction has executed. */
459 bool isExecuted() const { return status[Executed]; }
461 /** Sets this instruction as ready to commit. */
462 void setCanCommit() { status.set(CanCommit); }
464 /** Clears this instruction as being ready to commit. */
465 void clearCanCommit() { status.reset(CanCommit); }
467 /** Returns whether or not this instruction is ready to commit. */
468 bool readyToCommit() const { return status[CanCommit]; }
470 void setAtCommit() { status.set(AtCommit); }
472 bool isAtCommit() { return status[AtCommit]; }
474 /** Sets this instruction as committed. */
475 void setCommitted() { status.set(Committed); }
477 /** Returns whether or not this instruction is committed. */
478 bool isCommitted() const { return status[Committed]; }
480 /** Sets this instruction as squashed. */
481 void setSquashed() { status.set(Squashed); }
483 /** Returns whether or not this instruction is squashed. */
484 bool isSquashed() const { return status[Squashed]; }
486 //Instruction Queue Entry
487 //-----------------------
488 /** Sets this instruction as a entry the IQ. */
489 void setInIQ() { status.set(IqEntry); }
491 /** Sets this instruction as a entry the IQ. */
492 void clearInIQ() { status.reset(IqEntry); }
494 /** Returns whether or not this instruction has issued. */
495 bool isInIQ() const { return status[IqEntry]; }
497 /** Sets this instruction as squashed in the IQ. */
498 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
500 /** Returns whether or not this instruction is squashed in the IQ. */
501 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
504 //Load / Store Queue Functions
505 //-----------------------
506 /** Sets this instruction as a entry the LSQ. */
507 void setInLSQ() { status.set(LsqEntry); }
509 /** Sets this instruction as a entry the LSQ. */
510 void removeInLSQ() { status.reset(LsqEntry); }
512 /** Returns whether or not this instruction is in the LSQ. */
513 bool isInLSQ() const { return status[LsqEntry]; }
515 /** Sets this instruction as squashed in the LSQ. */
516 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
518 /** Returns whether or not this instruction is squashed in the LSQ. */
519 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
522 //Reorder Buffer Functions
523 //-----------------------
524 /** Sets this instruction as a entry the ROB. */
525 void setInROB() { status.set(RobEntry); }
527 /** Sets this instruction as a entry the ROB. */
528 void clearInROB() { status.reset(RobEntry); }
530 /** Returns whether or not this instruction is in the ROB. */
531 bool isInROB() const { return status[RobEntry]; }
533 /** Sets this instruction as squashed in the ROB. */
534 void setSquashedInROB() { status.set(SquashedInROB); }
536 /** Returns whether or not this instruction is squashed in the ROB. */
537 bool isSquashedInROB() const { return status[SquashedInROB]; }
539 /** Read the PC of this instruction. */
540 const Addr readPC() const { return PC; }
542 /** Set the next PC of this instruction (its actual target). */
543 void setNextPC(uint64_t val)
548 /** Sets the ASID. */
549 void setASID(short addr_space_id) { asid = addr_space_id; }
551 /** Sets the thread id. */
552 void setTid(unsigned tid) { threadNumber = tid; }
554 /** Sets the pointer to the thread state. */
555 void setThreadState(ImplState *state) { thread = state; }
557 /** Returns the thread context. */
558 ThreadContext *tcBase() { return thread->getTC(); }
561 /** Instruction effective address.
562 * @todo: Consider if this is necessary or not.
566 /** Whether or not the effective address calculation is completed.
567 * @todo: Consider if this is necessary or not.
572 /** Sets the effective address. */
573 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
575 /** Returns the effective address. */
576 const Addr &getEA() const { return instEffAddr; }
578 /** Returns whether or not the eff. addr. calculation has been completed. */
579 bool doneEACalc() { return eaCalcDone; }
581 /** Returns whether or not the eff. addr. source registers are ready. */
584 /** Whether or not the memory operation is done. */
588 /** Load queue index. */
591 /** Store queue index. */
594 /** Iterator pointing to this BaseDynInst in the list of all insts. */
597 /** Returns iterator to this instruction in the list of all insts. */
598 ListIt &getInstListIt() { return instListIt; }
600 /** Sets iterator for this instruction in the list of all insts. */
601 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
607 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
609 // Sometimes reads will get retried, so they may come through here
613 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
614 req->setThreadContext(thread->readCpuId(), threadNumber);
616 assert(addr == req->getVaddr());
619 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
620 TheISA::VMPageSize) {
621 return TheISA::genAlignmentFault();
624 fault = cpu->translateDataReadReq(req, thread);
626 if (fault == NoFault) {
627 effAddr = req->getVaddr();
628 physEffAddr = req->getPaddr();
629 memReqFlags = req->getFlags();
632 if (cpu->system->memctrl->badaddr(physEffAddr)) {
633 fault = TheISA::genMachineCheckFault();
637 fault = cpu->read(req, data, lqIdx);
640 fault = cpu->read(req, data, lqIdx);
643 // Return a fixed value to keep simulation deterministic even
644 // along misspeculated paths.
647 // Commit will have to clean up whatever happened. Set this
648 // instruction as executed.
653 traceData->setAddr(addr);
654 traceData->setData(data);
663 BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
666 traceData->setAddr(addr);
667 traceData->setData(data);
673 req->setVirt(asid, addr, sizeof(T), flags, this->PC);
674 req->setThreadContext(thread->readCpuId(), threadNumber);
676 if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
677 TheISA::VMPageSize) {
678 return TheISA::genAlignmentFault();
681 fault = cpu->translateDataWriteReq(req, thread);
683 if (fault == NoFault) {
684 effAddr = req->getVaddr();
685 physEffAddr = req->getPaddr();
686 memReqFlags = req->getFlags();
688 if (cpu->system->memctrl->badaddr(physEffAddr)) {
689 fault = TheISA::genMachineCheckFault();
691 fault = cpu->write(req, data, sqIdx);
694 fault = cpu->write(req, data, sqIdx);
699 // always return some result to keep misspeculated paths
700 // (which will ignore faults) deterministic
701 *res = (fault == NoFault) ? req->getScResult() : 0;
707 #endif // __CPU_BASE_DYN_INST_HH__