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45 #ifndef __CPU_BASE_DYN_INST_HH__
46 #define __CPU_BASE_DYN_INST_HH__
53 #include "arch/utility.hh"
54 #include "base/fast_alloc.hh"
55 #include "base/trace.hh"
56 #include "config/the_isa.hh"
57 #include "config/use_checker.hh"
58 #include "cpu/o3/comm.hh"
59 #include "cpu/exetrace.hh"
60 #include "cpu/inst_seq.hh"
61 #include "cpu/op_class.hh"
62 #include "cpu/static_inst.hh"
63 #include "cpu/translation.hh"
64 #include "mem/packet.hh"
65 #include "sim/byteswap.hh"
66 #include "sim/fault_fwd.hh"
67 #include "sim/system.hh"
72 * Defines a dynamic instruction context.
76 class BaseDynInst : public FastAlloc, public RefCounted
79 // Typedef for the CPU.
80 typedef typename Impl::CPUType ImplCPU;
81 typedef typename ImplCPU::ImplState ImplState;
83 // Logical register index type.
84 typedef TheISA::RegIndex RegIndex;
85 // Integer register type.
86 typedef TheISA::IntReg IntReg;
87 // Floating point register type.
88 typedef TheISA::FloatReg FloatReg;
90 // The DynInstPtr type.
91 typedef typename Impl::DynInstPtr DynInstPtr;
92 typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
94 // The list of instructions iterator type.
95 typedef typename std::list<DynInstPtr>::iterator ListIt;
98 MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
99 MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
102 /** The StaticInst used by this BaseDynInst. */
103 StaticInstPtr staticInst;
104 StaticInstPtr macroop;
106 ////////////////////////////////////////////
108 // INSTRUCTION EXECUTION
110 ////////////////////////////////////////////
111 /** InstRecord that tracks this instructions. */
112 Trace::InstRecord *traceData;
114 void demapPage(Addr vaddr, uint64_t asn)
116 cpu->demapPage(vaddr, asn);
118 void demapInstPage(Addr vaddr, uint64_t asn)
120 cpu->demapPage(vaddr, asn);
122 void demapDataPage(Addr vaddr, uint64_t asn)
124 cpu->demapPage(vaddr, asn);
127 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
129 Fault writeMem(uint8_t *data, unsigned size,
130 Addr addr, unsigned flags, uint64_t *res);
132 /** Splits a request in two if it crosses a dcache block. */
133 void splitRequest(RequestPtr req, RequestPtr &sreqLow,
134 RequestPtr &sreqHigh);
136 /** Initiate a DTB address translation. */
137 void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
138 RequestPtr sreqHigh, uint64_t *res,
141 /** Finish a DTB address translation. */
142 void finishTranslation(WholeTranslationState *state);
144 /** True if the DTB address translation has started. */
145 bool translationStarted;
147 /** True if the DTB address translation has completed. */
148 bool translationCompleted;
150 /** True if this address was found to match a previous load and they issued
151 * out of order. If that happend, then it's only a problem if an incoming
152 * snoop invalidate modifies the line, in which case we need to squash.
153 * If nothing modified the line the order doesn't matter.
155 bool possibleLoadViolation;
157 /** True if the address hit a external snoop while sitting in the LSQ.
158 * If this is true and a older instruction sees it, this instruction must
161 bool hitExternalSnoop;
164 * Returns true if the DTB address translation is being delayed due to a hw
167 bool isTranslationDelayed() const
169 return (translationStarted && !translationCompleted);
173 * Saved memory requests (needed when the DTB address translation is
174 * delayed due to a hw page table walk).
177 RequestPtr savedSreqLow;
178 RequestPtr savedSreqHigh;
181 // Need a copy of main request pointer to verify on writes.
182 RequestPtr reqToVerify;
185 /** @todo: Consider making this private. */
187 /** The sequence number of the instruction. */
191 IqEntry, /// Instruction is in the IQ
192 RobEntry, /// Instruction is in the ROB
193 LsqEntry, /// Instruction is in the LSQ
194 Completed, /// Instruction has completed
195 ResultReady, /// Instruction has its result
196 CanIssue, /// Instruction can issue and execute
197 Issued, /// Instruction has issued
198 Executed, /// Instruction has executed
199 CanCommit, /// Instruction can commit
200 AtCommit, /// Instruction has reached commit
201 Committed, /// Instruction has committed
202 Squashed, /// Instruction is squashed
203 SquashedInIQ, /// Instruction is squashed in the IQ
204 SquashedInLSQ, /// Instruction is squashed in the LSQ
205 SquashedInROB, /// Instruction is squashed in the ROB
206 RecoverInst, /// Is a recover instruction
207 BlockingInst, /// Is a blocking instruction
208 ThreadsyncWait, /// Is a thread synchronization instruction
209 SerializeBefore, /// Needs to serialize on
210 /// instructions ahead of it
211 SerializeAfter, /// Needs to serialize instructions behind it
212 SerializeHandled, /// Serialization has been handled
216 /** The status of this BaseDynInst. Several bits can be set. */
217 std::bitset<NumStatus> status;
219 /** The thread this instruction is from. */
220 ThreadID threadNumber;
222 /** data address space ID, for loads & stores. */
225 /** How many source registers are ready. */
228 /** Pointer to the Impl's CPU object. */
231 /** Pointer to the thread state. */
234 /** The kind of fault this instruction has generated. */
237 /** Pointer to the data for the memory access. */
240 /** The effective virtual address (lds & stores only). */
243 /** The size of the request */
246 /** Is the effective virtual address valid. */
249 /** The effective physical address. */
252 /** The memory request flags (from translation). */
253 unsigned memReqFlags;
258 void set(uint64_t i) { integer = i; }
259 void set(double d) { dbl = d; }
260 void get(uint64_t& i) { i = integer; }
261 void get(double& d) { d = dbl; }
264 /** The result of the instruction; assumes an instruction can have many
265 * destination registers.
267 std::queue<Result> instResult;
269 /** Records changes to result? */
272 /** Did this instruction execute, or is it predicated false */
276 /** PC state for this instruction. */
279 /** Predicted PC state after this instruction. */
280 TheISA::PCState predPC;
282 /** If this is a branch that was predicted taken */
291 /** Whether or not the source register is ready.
292 * @todo: Not sure this should be here vs the derived class.
294 bool _readySrcRegIdx[MaxInstSrcRegs];
297 /** Flattened register index of the destination registers of this
300 TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
302 /** Flattened register index of the source registers of this
305 TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
307 /** Physical register index of the destination registers of this
310 PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
312 /** Physical register index of the source registers of this
315 PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
317 /** Physical register index of the previous producers of the
318 * architected destinations.
320 PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
324 /** Returns the physical register index of the i'th destination
327 PhysRegIndex renamedDestRegIdx(int idx) const
329 return _destRegIdx[idx];
332 /** Returns the physical register index of the i'th source register. */
333 PhysRegIndex renamedSrcRegIdx(int idx) const
335 return _srcRegIdx[idx];
338 /** Returns the flattened register index of the i'th destination
341 TheISA::RegIndex flattenedDestRegIdx(int idx) const
343 return _flatDestRegIdx[idx];
346 /** Returns the flattened register index of the i'th source register */
347 TheISA::RegIndex flattenedSrcRegIdx(int idx) const
349 return _flatSrcRegIdx[idx];
352 /** Returns the physical register index of the previous physical register
353 * that remapped to the same logical register index.
355 PhysRegIndex prevDestRegIdx(int idx) const
357 return _prevDestRegIdx[idx];
360 /** Renames a destination register to a physical register. Also records
361 * the previous physical register that the logical register mapped to.
363 void renameDestReg(int idx,
364 PhysRegIndex renamed_dest,
365 PhysRegIndex previous_rename)
367 _destRegIdx[idx] = renamed_dest;
368 _prevDestRegIdx[idx] = previous_rename;
371 /** Renames a source logical register to the physical register which
372 * has/will produce that logical register's result.
373 * @todo: add in whether or not the source register is ready.
375 void renameSrcReg(int idx, PhysRegIndex renamed_src)
377 _srcRegIdx[idx] = renamed_src;
380 /** Flattens a source architectural register index into a logical index.
382 void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
384 _flatSrcRegIdx[idx] = flattened_src;
387 /** Flattens a destination architectural register index into a logical
390 void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
392 _flatDestRegIdx[idx] = flattened_dest;
394 /** BaseDynInst constructor given a binary instruction.
395 * @param staticInst A StaticInstPtr to the underlying instruction.
396 * @param pc The PC state for the instruction.
397 * @param predPC The predicted next PC state for the instruction.
398 * @param seq_num The sequence number of the instruction.
399 * @param cpu Pointer to the instruction's CPU.
401 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
402 TheISA::PCState pc, TheISA::PCState predPC,
403 InstSeqNum seq_num, ImplCPU *cpu);
405 /** BaseDynInst constructor given a StaticInst pointer.
406 * @param _staticInst The StaticInst for this BaseDynInst.
408 BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
410 /** BaseDynInst destructor. */
414 /** Function to initialize variables in the constructors. */
418 /** Dumps out contents of this BaseDynInst. */
421 /** Dumps out contents of this BaseDynInst into given string. */
422 void dump(std::string &outstring);
424 /** Read this CPU's ID. */
425 int cpuId() { return cpu->cpuId(); }
427 /** Read this context's system-wide ID **/
428 int contextId() { return thread->contextId(); }
430 /** Returns the fault type. */
431 Fault getFault() { return fault; }
433 /** Checks whether or not this instruction has had its branch target
434 * calculated yet. For now it is not utilized and is hacked to be
436 * @todo: Actually use this instruction.
438 bool doneTargCalc() { return false; }
440 /** Set the predicted target of this current instruction. */
441 void setPredTarg(const TheISA::PCState &_predPC)
446 const TheISA::PCState &readPredTarg() { return predPC; }
448 /** Returns the predicted PC immediately after the branch. */
449 Addr predInstAddr() { return predPC.instAddr(); }
451 /** Returns the predicted PC two instructions after the branch */
452 Addr predNextInstAddr() { return predPC.nextInstAddr(); }
454 /** Returns the predicted micro PC after the branch */
455 Addr predMicroPC() { return predPC.microPC(); }
457 /** Returns whether the instruction was predicted taken or not. */
463 void setPredTaken(bool predicted_taken)
465 predTaken = predicted_taken;
468 /** Returns whether the instruction mispredicted. */
471 TheISA::PCState tempPC = pc;
472 TheISA::advancePC(tempPC, staticInst);
473 return !(tempPC == predPC);
477 // Instruction types. Forward checks to StaticInst object.
479 bool isNop() const { return staticInst->isNop(); }
480 bool isMemRef() const { return staticInst->isMemRef(); }
481 bool isLoad() const { return staticInst->isLoad(); }
482 bool isStore() const { return staticInst->isStore(); }
483 bool isStoreConditional() const
484 { return staticInst->isStoreConditional(); }
485 bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
486 bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
487 bool isInteger() const { return staticInst->isInteger(); }
488 bool isFloating() const { return staticInst->isFloating(); }
489 bool isControl() const { return staticInst->isControl(); }
490 bool isCall() const { return staticInst->isCall(); }
491 bool isReturn() const { return staticInst->isReturn(); }
492 bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
493 bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
494 bool isCondCtrl() const { return staticInst->isCondCtrl(); }
495 bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
496 bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
497 bool isThreadSync() const { return staticInst->isThreadSync(); }
498 bool isSerializing() const { return staticInst->isSerializing(); }
499 bool isSerializeBefore() const
500 { return staticInst->isSerializeBefore() || status[SerializeBefore]; }
501 bool isSerializeAfter() const
502 { return staticInst->isSerializeAfter() || status[SerializeAfter]; }
503 bool isSquashAfter() const { return staticInst->isSquashAfter(); }
504 bool isMemBarrier() const { return staticInst->isMemBarrier(); }
505 bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
506 bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
507 bool isQuiesce() const { return staticInst->isQuiesce(); }
508 bool isIprAccess() const { return staticInst->isIprAccess(); }
509 bool isUnverifiable() const { return staticInst->isUnverifiable(); }
510 bool isSyscall() const { return staticInst->isSyscall(); }
511 bool isMacroop() const { return staticInst->isMacroop(); }
512 bool isMicroop() const { return staticInst->isMicroop(); }
513 bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
514 bool isLastMicroop() const { return staticInst->isLastMicroop(); }
515 bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
516 bool isMicroBranch() const { return staticInst->isMicroBranch(); }
518 /** Temporarily sets this instruction as a serialize before instruction. */
519 void setSerializeBefore() { status.set(SerializeBefore); }
521 /** Clears the serializeBefore part of this instruction. */
522 void clearSerializeBefore() { status.reset(SerializeBefore); }
524 /** Checks if this serializeBefore is only temporarily set. */
525 bool isTempSerializeBefore() { return status[SerializeBefore]; }
527 /** Temporarily sets this instruction as a serialize after instruction. */
528 void setSerializeAfter() { status.set(SerializeAfter); }
530 /** Clears the serializeAfter part of this instruction.*/
531 void clearSerializeAfter() { status.reset(SerializeAfter); }
533 /** Checks if this serializeAfter is only temporarily set. */
534 bool isTempSerializeAfter() { return status[SerializeAfter]; }
536 /** Sets the serialization part of this instruction as handled. */
537 void setSerializeHandled() { status.set(SerializeHandled); }
539 /** Checks if the serialization part of this instruction has been
540 * handled. This does not apply to the temporary serializing
541 * state; it only applies to this instruction's own permanent
544 bool isSerializeHandled() { return status[SerializeHandled]; }
546 /** Returns the opclass of this instruction. */
547 OpClass opClass() const { return staticInst->opClass(); }
549 /** Returns the branch target address. */
550 TheISA::PCState branchTarget() const
551 { return staticInst->branchTarget(pc); }
553 /** Returns the number of source registers. */
554 int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
556 /** Returns the number of destination registers. */
557 int8_t numDestRegs() const { return staticInst->numDestRegs(); }
559 // the following are used to track physical register usage
560 // for machines with separate int & FP reg files
561 int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
562 int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
564 /** Returns the logical register index of the i'th destination register. */
565 RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
567 /** Returns the logical register index of the i'th source register. */
568 RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
570 /** Pops a result off the instResult queue */
574 if (!instResult.empty()) {
575 instResult.front().get(t);
580 /** Read the most recent result stored by this instruction */
582 void readResult(T& t)
584 instResult.back().get(t);
587 /** Pushes a result onto the instResult queue */
594 instResult.push(instRes);
598 /** Records an integer register being set to a value. */
599 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
601 setResult<uint64_t>(val);
604 /** Records an fp register being set to a value. */
605 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
608 if (width == 32 || width == 64) {
609 setResult<double>(val);
611 panic("Unsupported width!");
615 /** Records an fp register being set to a value. */
616 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
618 setResult<double>(val);
621 /** Records an fp register being set to an integer value. */
622 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
625 setResult<uint64_t>(val);
628 /** Records an fp register being set to an integer value. */
629 void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
631 setResult<uint64_t>(val);
634 /** Records that one of the source registers is ready. */
635 void markSrcRegReady();
637 /** Marks a specific register as ready. */
638 void markSrcRegReady(RegIndex src_idx);
640 /** Returns if a source register is ready. */
641 bool isReadySrcRegIdx(int idx) const
643 return this->_readySrcRegIdx[idx];
646 /** Sets this instruction as completed. */
647 void setCompleted() { status.set(Completed); }
649 /** Returns whether or not this instruction is completed. */
650 bool isCompleted() const { return status[Completed]; }
652 /** Marks the result as ready. */
653 void setResultReady() { status.set(ResultReady); }
655 /** Returns whether or not the result is ready. */
656 bool isResultReady() const { return status[ResultReady]; }
658 /** Sets this instruction as ready to issue. */
659 void setCanIssue() { status.set(CanIssue); }
661 /** Returns whether or not this instruction is ready to issue. */
662 bool readyToIssue() const { return status[CanIssue]; }
664 /** Clears this instruction being able to issue. */
665 void clearCanIssue() { status.reset(CanIssue); }
667 /** Sets this instruction as issued from the IQ. */
668 void setIssued() { status.set(Issued); }
670 /** Returns whether or not this instruction has issued. */
671 bool isIssued() const { return status[Issued]; }
673 /** Clears this instruction as being issued. */
674 void clearIssued() { status.reset(Issued); }
676 /** Sets this instruction as executed. */
677 void setExecuted() { status.set(Executed); }
679 /** Returns whether or not this instruction has executed. */
680 bool isExecuted() const { return status[Executed]; }
682 /** Sets this instruction as ready to commit. */
683 void setCanCommit() { status.set(CanCommit); }
685 /** Clears this instruction as being ready to commit. */
686 void clearCanCommit() { status.reset(CanCommit); }
688 /** Returns whether or not this instruction is ready to commit. */
689 bool readyToCommit() const { return status[CanCommit]; }
691 void setAtCommit() { status.set(AtCommit); }
693 bool isAtCommit() { return status[AtCommit]; }
695 /** Sets this instruction as committed. */
696 void setCommitted() { status.set(Committed); }
698 /** Returns whether or not this instruction is committed. */
699 bool isCommitted() const { return status[Committed]; }
701 /** Sets this instruction as squashed. */
702 void setSquashed() { status.set(Squashed); }
704 /** Returns whether or not this instruction is squashed. */
705 bool isSquashed() const { return status[Squashed]; }
707 //Instruction Queue Entry
708 //-----------------------
709 /** Sets this instruction as a entry the IQ. */
710 void setInIQ() { status.set(IqEntry); }
712 /** Sets this instruction as a entry the IQ. */
713 void clearInIQ() { status.reset(IqEntry); }
715 /** Returns whether or not this instruction has issued. */
716 bool isInIQ() const { return status[IqEntry]; }
718 /** Sets this instruction as squashed in the IQ. */
719 void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
721 /** Returns whether or not this instruction is squashed in the IQ. */
722 bool isSquashedInIQ() const { return status[SquashedInIQ]; }
725 //Load / Store Queue Functions
726 //-----------------------
727 /** Sets this instruction as a entry the LSQ. */
728 void setInLSQ() { status.set(LsqEntry); }
730 /** Sets this instruction as a entry the LSQ. */
731 void removeInLSQ() { status.reset(LsqEntry); }
733 /** Returns whether or not this instruction is in the LSQ. */
734 bool isInLSQ() const { return status[LsqEntry]; }
736 /** Sets this instruction as squashed in the LSQ. */
737 void setSquashedInLSQ() { status.set(SquashedInLSQ);}
739 /** Returns whether or not this instruction is squashed in the LSQ. */
740 bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
743 //Reorder Buffer Functions
744 //-----------------------
745 /** Sets this instruction as a entry the ROB. */
746 void setInROB() { status.set(RobEntry); }
748 /** Sets this instruction as a entry the ROB. */
749 void clearInROB() { status.reset(RobEntry); }
751 /** Returns whether or not this instruction is in the ROB. */
752 bool isInROB() const { return status[RobEntry]; }
754 /** Sets this instruction as squashed in the ROB. */
755 void setSquashedInROB() { status.set(SquashedInROB); }
757 /** Returns whether or not this instruction is squashed in the ROB. */
758 bool isSquashedInROB() const { return status[SquashedInROB]; }
760 /** Read the PC state of this instruction. */
761 const TheISA::PCState pcState() const { return pc; }
763 /** Set the PC state of this instruction. */
764 const void pcState(const TheISA::PCState &val) { pc = val; }
766 /** Read the PC of this instruction. */
767 const Addr instAddr() const { return pc.instAddr(); }
769 /** Read the PC of the next instruction. */
770 const Addr nextInstAddr() const { return pc.nextInstAddr(); }
772 /**Read the micro PC of this instruction. */
773 const Addr microPC() const { return pc.microPC(); }
780 void setPredicate(bool val)
785 traceData->setPredicate(val);
789 /** Sets the ASID. */
790 void setASID(short addr_space_id) { asid = addr_space_id; }
792 /** Sets the thread id. */
793 void setTid(ThreadID tid) { threadNumber = tid; }
795 /** Sets the pointer to the thread state. */
796 void setThreadState(ImplState *state) { thread = state; }
798 /** Returns the thread context. */
799 ThreadContext *tcBase() { return thread->getTC(); }
802 /** Instruction effective address.
803 * @todo: Consider if this is necessary or not.
807 /** Whether or not the effective address calculation is completed.
808 * @todo: Consider if this is necessary or not.
812 /** Is this instruction's memory access uncacheable. */
815 /** Has this instruction generated a memory request. */
819 /** Sets the effective address. */
820 void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
822 /** Returns the effective address. */
823 const Addr &getEA() const { return instEffAddr; }
825 /** Returns whether or not the eff. addr. calculation has been completed. */
826 bool doneEACalc() { return eaCalcDone; }
828 /** Returns whether or not the eff. addr. source registers are ready. */
831 /** Whether or not the memory operation is done. */
834 /** Is this instruction's memory access uncacheable. */
835 bool uncacheable() { return isUncacheable; }
837 /** Has this instruction generated a memory request. */
838 bool hasRequest() { return reqMade; }
841 /** Load queue index. */
844 /** Store queue index. */
847 /** Iterator pointing to this BaseDynInst in the list of all insts. */
850 /** Returns iterator to this instruction in the list of all insts. */
851 ListIt &getInstListIt() { return instListIt; }
853 /** Sets iterator for this instruction in the list of all insts. */
854 void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
857 /** Returns the number of consecutive store conditional failures. */
858 unsigned readStCondFailures()
859 { return thread->storeCondFailures; }
861 /** Sets the number of consecutive store conditional failures. */
862 void setStCondFailures(unsigned sc_failures)
863 { thread->storeCondFailures = sc_failures; }
868 BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
869 unsigned size, unsigned flags)
873 Request *sreqLow = NULL;
874 Request *sreqHigh = NULL;
876 if (reqMade && translationStarted) {
878 sreqLow = savedSreqLow;
879 sreqHigh = savedSreqHigh;
881 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
882 thread->contextId(), threadNumber);
884 // Only split the request if the ISA supports unaligned accesses.
885 if (TheISA::HasUnalignedMemAcc) {
886 splitRequest(req, sreqLow, sreqHigh);
888 initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
891 if (translationCompleted) {
892 if (fault == NoFault) {
893 effAddr = req->getVaddr();
897 if (reqToVerify != NULL) {
900 reqToVerify = new Request(*req);
902 fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
904 // Commit will have to clean up whatever happened. Set this
905 // instruction as executed.
909 if (fault != NoFault) {
910 // Return a fixed value to keep simulation deterministic even
911 // along misspeculated paths.
918 traceData->setAddr(addr);
926 BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
927 Addr addr, unsigned flags, uint64_t *res)
930 traceData->setAddr(addr);
935 Request *sreqLow = NULL;
936 Request *sreqHigh = NULL;
938 if (reqMade && translationStarted) {
940 sreqLow = savedSreqLow;
941 sreqHigh = savedSreqHigh;
943 req = new Request(asid, addr, size, flags, this->pc.instAddr(),
944 thread->contextId(), threadNumber);
946 // Only split the request if the ISA supports unaligned accesses.
947 if (TheISA::HasUnalignedMemAcc) {
948 splitRequest(req, sreqLow, sreqHigh);
950 initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
953 if (fault == NoFault && translationCompleted) {
954 effAddr = req->getVaddr();
958 if (reqToVerify != NULL) {
961 reqToVerify = new Request(*req);
962 #endif // USE_CHECKER
963 fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
971 BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
972 RequestPtr &sreqHigh)
974 // Check to see if the request crosses the next level block boundary.
975 unsigned block_size = cpu->getDcachePort()->peerBlockSize();
976 Addr addr = req->getVaddr();
977 Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
978 assert(split_addr <= addr || split_addr - addr < block_size);
981 if (split_addr > addr) {
982 req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
988 BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
989 RequestPtr sreqHigh, uint64_t *res,
992 translationStarted = true;
994 if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
995 WholeTranslationState *state =
996 new WholeTranslationState(req, NULL, res, mode);
998 // One translation if the request isn't split.
999 DataTranslation<BaseDynInstPtr> *trans =
1000 new DataTranslation<BaseDynInstPtr>(this, state);
1001 cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
1002 if (!translationCompleted) {
1003 // Save memory requests.
1004 savedReq = state->mainReq;
1005 savedSreqLow = state->sreqLow;
1006 savedSreqHigh = state->sreqHigh;
1009 WholeTranslationState *state =
1010 new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
1012 // Two translations when the request is split.
1013 DataTranslation<BaseDynInstPtr> *stransLow =
1014 new DataTranslation<BaseDynInstPtr>(this, state, 0);
1015 DataTranslation<BaseDynInstPtr> *stransHigh =
1016 new DataTranslation<BaseDynInstPtr>(this, state, 1);
1018 cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
1019 cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
1020 if (!translationCompleted) {
1021 // Save memory requests.
1022 savedReq = state->mainReq;
1023 savedSreqLow = state->sreqLow;
1024 savedSreqHigh = state->sreqHigh;
1029 template<class Impl>
1031 BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
1033 fault = state->getFault();
1035 if (state->isUncacheable())
1036 isUncacheable = true;
1038 if (fault == NoFault) {
1039 physEffAddr = state->getPaddr();
1040 memReqFlags = state->getFlags();
1042 if (state->mainReq->isCondSwap()) {
1044 state->mainReq->setExtraData(*state->res);
1048 state->deleteReqs();
1052 translationCompleted = true;
1055 #endif // __CPU_BASE_DYN_INST_HH__