src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #include <iostream>
  44 #include <set>
  45 #include <sstream>
  46 #include <string>
  47
  48 #include "base/cprintf.hh"
  49 #include "base/trace.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base_dyn_inst.hh"
  52 #include "cpu/exetrace.hh"
  53 #include "debug/DynInst.hh"
  54 #include "debug/IQ.hh"
  55 #include "mem/request.hh"
  56 #include "sim/faults.hh"
  57
  58 #define NOHASH
  59 #ifndef NOHASH
  60
  61 #include "base/hashmap.hh"
  62
  63 unsigned int MyHashFunc(const BaseDynInst *addr)
  64 {
  65     unsigned a = (unsigned)addr;
  66     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
  67
  68     return hash;
  69 }
  70
  71 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
  72 my_hash_t;
  73
  74 my_hash_t thishash;
  75 #endif
  76
  77 template <class Impl>
  78 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  79                                TheISA::PCState _pc, TheISA::PCState _predPC,
  80                                InstSeqNum seq_num, ImplCPU *cpu)
  81   : staticInst(_staticInst), traceData(NULL), cpu(cpu)
  82 {
  83     seqNum = seq_num;
  84
  85     pc = _pc;
  86     predPC = _predPC;
  87     predTaken = false;
  88
  89     initVars();
  90 }
  91
  92 template <class Impl>
  93 BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
  94                                TheISA::PCState _pc, TheISA::PCState _predPC,
  95                                InstSeqNum seq_num, ImplCPU *cpu)
  96   : staticInst(inst, _pc.instAddr()), traceData(NULL), cpu(cpu)
  97 {
  98     seqNum = seq_num;
  99
 100     pc = _pc;
 101     predPC = _predPC;
 102     predTaken = false;
 103
 104     initVars();
 105 }
 106
 107 template <class Impl>
 108 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
 109     : staticInst(_staticInst), traceData(NULL)
 110 {
 111     seqNum = 0;
 112     initVars();
 113 }
 114
 115 template <class Impl>
 116 void
 117 BaseDynInst<Impl>::initVars()
 118 {
 119     memData = NULL;
 120     effAddr = 0;
 121     effAddrValid = false;
 122     physEffAddr = 0;
 123
 124     translationStarted = false;
 125     translationCompleted = false;
 126
 127     isUncacheable = false;
 128     reqMade = false;
 129     readyRegs = 0;
 130
 131     instResult.integer = 0;
 132     recordResult = true;
 133
 134     status.reset();
 135
 136     eaCalcDone = false;
 137     memOpDone = false;
 138     predicate = true;
 139
 140     lqIdx = -1;
 141     sqIdx = -1;
 142
 143     // Eventually make this a parameter.
 144     threadNumber = 0;
 145
 146     // Also make this a parameter, or perhaps get it from xc or cpu.
 147     asid = 0;
 148
 149     // Initialize the fault to be NoFault.
 150     fault = NoFault;
 151
 152 #ifndef NDEBUG
 153     ++cpu->instcount;
 154
 155     if (cpu->instcount > 1500) {
 156 #ifdef DEBUG
 157         cpu->dumpInsts();
 158         dumpSNList();
 159 #endif
 160         assert(cpu->instcount <= 1500);
 161     }
 162
 163     DPRINTF(DynInst,
 164         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 165         seqNum, cpu->name(), cpu->instcount);
 166 #endif
 167
 168 #ifdef DEBUG
 169     cpu->snList.insert(seqNum);
 170 #endif
 171 }
 172
 173 template <class Impl>
 174 BaseDynInst<Impl>::~BaseDynInst()
 175 {
 176     if (memData) {
 177         delete [] memData;
 178     }
 179
 180     if (traceData) {
 181         delete traceData;
 182     }
 183
 184     fault = NoFault;
 185
 186 #ifndef NDEBUG
 187     --cpu->instcount;
 188
 189     DPRINTF(DynInst,
 190         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 191         seqNum, cpu->name(), cpu->instcount);
 192 #endif
 193 #ifdef DEBUG
 194     cpu->snList.erase(seqNum);
 195 #endif
 196 }
 197
 198 #ifdef DEBUG
 199 template <class Impl>
 200 void
 201 BaseDynInst<Impl>::dumpSNList()
 202 {
 203     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 204
 205     int count = 0;
 206     while (sn_it != cpu->snList.end()) {
 207         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 208         count++;
 209         sn_it++;
 210     }
 211 }
 212 #endif
 213
 214 template <class Impl>
 215 void
 216 BaseDynInst<Impl>::dump()
 217 {
 218     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 219     std::cout << staticInst->disassemble(pc.instAddr());
 220     cprintf("'\n");
 221 }
 222
 223 template <class Impl>
 224 void
 225 BaseDynInst<Impl>::dump(std::string &outstring)
 226 {
 227     std::ostringstream s;
 228     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 229       << staticInst->disassemble(pc.instAddr());
 230
 231     outstring = s.str();
 232 }
 233
 234 template <class Impl>
 235 void
 236 BaseDynInst<Impl>::markSrcRegReady()
 237 {
 238     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 239             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 240     if (++readyRegs == numSrcRegs()) {
 241         setCanIssue();
 242     }
 243 }
 244
 245 template <class Impl>
 246 void
 247 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 248 {
 249     _readySrcRegIdx[src_idx] = true;
 250
 251     markSrcRegReady();
 252 }
 253
 254 template <class Impl>
 255 bool
 256 BaseDynInst<Impl>::eaSrcsReady()
 257 {
 258     // For now I am assuming that src registers 1..n-1 are the ones that the
 259     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 260     // stored)
 261
 262     for (int i = 1; i < numSrcRegs(); ++i) {
 263         if (!_readySrcRegIdx[i])
 264             return false;
 265     }
 266
 267     return true;
 268 }