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36 #include "base/cprintf.hh"
37 #include "base/trace.hh"
39 #include "sim/faults.hh"
40 #include "cpu/exetrace.hh"
41 #include "mem/request.hh"
43 #include "cpu/base_dyn_inst.hh"
48 #include "base/hashmap.hh"
50 unsigned int MyHashFunc(const BaseDynInst *addr)
52 unsigned a = (unsigned)addr;
53 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
58 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
65 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
66 Addr inst_PC, Addr inst_NPC,
68 Addr pred_PC, Addr pred_NPC,
70 InstSeqNum seq_num, ImplCPU *cpu)
71 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
76 staticInst->isMicroop() && !staticInst->isLastMicroop();
79 microPC = inst_MicroPC;
83 nextMicroPC = microPC + 1;
86 nextNPC = nextPC + sizeof(TheISA::MachInst);
91 predMicroPC = pred_MicroPC;
98 BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
99 Addr inst_PC, Addr inst_NPC,
101 Addr pred_PC, Addr pred_NPC,
103 InstSeqNum seq_num, ImplCPU *cpu)
104 : staticInst(inst, inst_PC), traceData(NULL), cpu(cpu)
109 staticInst->isMicroop() && !staticInst->isLastMicroop();
112 microPC = inst_MicroPC;
116 nextMicroPC = microPC + 1;
119 nextNPC = nextPC + sizeof(TheISA::MachInst);
124 predMicroPC = pred_MicroPC;
130 template <class Impl>
131 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
132 : staticInst(_staticInst), traceData(NULL)
138 template <class Impl>
140 BaseDynInst<Impl>::initVars()
144 effAddrValid = false;
147 isUncacheable = false;
151 instResult.integer = 0;
162 // Eventually make this a parameter.
165 // Also make this a parameter, or perhaps get it from xc or cpu.
168 // Initialize the fault to be NoFault.
173 if (instcount > 1500) {
178 assert(instcount <= 1500);
181 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
185 cpu->snList.insert(seqNum);
189 template <class Impl>
190 BaseDynInst<Impl>::~BaseDynInst()
204 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
207 cpu->snList.erase(seqNum);
212 template <class Impl>
214 BaseDynInst<Impl>::dumpSNList()
216 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
219 while (sn_it != cpu->snList.end()) {
220 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
227 template <class Impl>
229 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
231 // This is the "functional" implementation of prefetch. Not much
232 // happens here since prefetches don't affect the architectural
235 // Generate a MemReq so we can translate the effective address.
236 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
239 // Prefetches never cause faults.
242 // note this is a local, not BaseDynInst::fault
243 Fault trans_fault = cpu->translateDataReadReq(req);
245 if (trans_fault == NoFault && !(req->isUncacheable())) {
246 // It's a valid address to cacheable space. Record key MemReq
247 // parameters so we can generate another one just like it for
248 // the timing access without calling translate() again (which
249 // might mess up the TLB).
250 effAddr = req->vaddr;
251 physEffAddr = req->paddr;
252 memReqFlags = req->flags;
254 // Bogus address (invalid or uncacheable space). Mark it by
255 // setting the eff_addr to InvalidAddr.
256 effAddr = physEffAddr = MemReq::inval_addr;
260 traceData->setAddr(addr);
265 template <class Impl>
267 BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
269 // Not currently supported.
273 * @todo Need to find a way to get the cache block size here.
275 template <class Impl>
277 BaseDynInst<Impl>::copySrcTranslate(Addr src)
279 // Not currently supported.
284 * @todo Need to find a way to get the cache block size here.
286 template <class Impl>
288 BaseDynInst<Impl>::copy(Addr dest)
290 // Not currently supported.
294 template <class Impl>
296 BaseDynInst<Impl>::dump()
298 cprintf("T%d : %#08d `", threadNumber, PC);
299 std::cout << staticInst->disassemble(PC);
303 template <class Impl>
305 BaseDynInst<Impl>::dump(std::string &outstring)
307 std::ostringstream s;
308 s << "T" << threadNumber << " : 0x" << PC << " "
309 << staticInst->disassemble(PC);
314 template <class Impl>
316 BaseDynInst<Impl>::markSrcRegReady()
318 if (++readyRegs == numSrcRegs()) {
323 template <class Impl>
325 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
327 _readySrcRegIdx[src_idx] = true;
332 template <class Impl>
334 BaseDynInst<Impl>::eaSrcsReady()
336 // For now I am assuming that src registers 1..n-1 are the ones that the
337 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
340 for (int i = 1; i < numSrcRegs(); ++i) {
341 if (!_readySrcRegIdx[i])