src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #include <iostream>
  44 #include <set>
  45 #include <sstream>
  46 #include <string>
  47
  48 #include "base/cprintf.hh"
  49 #include "base/trace.hh"
  50 #include "config/the_isa.hh"
  51 #include "config/use_checker.hh"
  52 #include "cpu/base_dyn_inst.hh"
  53 #include "cpu/exetrace.hh"
  54 #include "debug/DynInst.hh"
  55 #include "debug/IQ.hh"
  56 #include "mem/request.hh"
  57 #include "sim/faults.hh"
  58
  59 template <class Impl>
  60 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  61                                StaticInstPtr _macroop,
  62                                TheISA::PCState _pc, TheISA::PCState _predPC,
  63                                InstSeqNum seq_num, ImplCPU *cpu)
  64   : staticInst(_staticInst), macroop(_macroop), traceData(NULL), cpu(cpu)
  65 {
  66     seqNum = seq_num;
  67
  68     pc = _pc;
  69     predPC = _predPC;
  70     predTaken = false;
  71
  72     initVars();
  73 }
  74
  75 template <class Impl>
  76 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  77                                StaticInstPtr _macroop)
  78     : staticInst(_staticInst), macroop(_macroop), traceData(NULL)
  79 {
  80     seqNum = 0;
  81     initVars();
  82 }
  83
  84 template <class Impl>
  85 void
  86 BaseDynInst<Impl>::initVars()
  87 {
  88     memData = NULL;
  89     effAddr = 0;
  90     effAddrValid = false;
  91     physEffAddr = 0;
  92
  93     translationStarted = false;
  94     translationCompleted = false;
  95     possibleLoadViolation = false;
  96     hitExternalSnoop  = false;
  97
  98     isUncacheable = false;
  99     reqMade = false;
 100     readyRegs = 0;
 101
 102     recordResult = true;
 103
 104     status.reset();
 105
 106     eaCalcDone = false;
 107     memOpDone = false;
 108     predicate = true;
 109
 110     lqIdx = -1;
 111     sqIdx = -1;
 112
 113     // Eventually make this a parameter.
 114     threadNumber = 0;
 115
 116     // Also make this a parameter, or perhaps get it from xc or cpu.
 117     asid = 0;
 118
 119     // Initialize the fault to be NoFault.
 120     fault = NoFault;
 121
 122 #ifndef NDEBUG
 123     ++cpu->instcount;
 124
 125     if (cpu->instcount > 1500) {
 126 #ifdef DEBUG
 127         cpu->dumpInsts();
 128         dumpSNList();
 129 #endif
 130         assert(cpu->instcount <= 1500);
 131     }
 132
 133     DPRINTF(DynInst,
 134         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 135         seqNum, cpu->name(), cpu->instcount);
 136 #endif
 137
 138 #ifdef DEBUG
 139     cpu->snList.insert(seqNum);
 140 #endif
 141
 142 #if USE_CHECKER
 143     reqToVerify = NULL;
 144 #endif
 145 }
 146
 147 template <class Impl>
 148 BaseDynInst<Impl>::~BaseDynInst()
 149 {
 150     if (memData) {
 151         delete [] memData;
 152     }
 153
 154     if (traceData) {
 155         delete traceData;
 156     }
 157
 158     fault = NoFault;
 159
 160 #ifndef NDEBUG
 161     --cpu->instcount;
 162
 163     DPRINTF(DynInst,
 164         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 165         seqNum, cpu->name(), cpu->instcount);
 166 #endif
 167 #ifdef DEBUG
 168     cpu->snList.erase(seqNum);
 169 #endif
 170
 171 #if USE_CHECKER
 172     if (reqToVerify)
 173         delete reqToVerify;
 174 #endif // USE_CHECKER
 175 }
 176
 177 #ifdef DEBUG
 178 template <class Impl>
 179 void
 180 BaseDynInst<Impl>::dumpSNList()
 181 {
 182     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 183
 184     int count = 0;
 185     while (sn_it != cpu->snList.end()) {
 186         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 187         count++;
 188         sn_it++;
 189     }
 190 }
 191 #endif
 192
 193 template <class Impl>
 194 void
 195 BaseDynInst<Impl>::dump()
 196 {
 197     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 198     std::cout << staticInst->disassemble(pc.instAddr());
 199     cprintf("'\n");
 200 }
 201
 202 template <class Impl>
 203 void
 204 BaseDynInst<Impl>::dump(std::string &outstring)
 205 {
 206     std::ostringstream s;
 207     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 208       << staticInst->disassemble(pc.instAddr());
 209
 210     outstring = s.str();
 211 }
 212
 213 template <class Impl>
 214 void
 215 BaseDynInst<Impl>::markSrcRegReady()
 216 {
 217     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 218             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 219     if (++readyRegs == numSrcRegs()) {
 220         setCanIssue();
 221     }
 222 }
 223
 224 template <class Impl>
 225 void
 226 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 227 {
 228     _readySrcRegIdx[src_idx] = true;
 229
 230     markSrcRegReady();
 231 }
 232
 233 template <class Impl>
 234 bool
 235 BaseDynInst<Impl>::eaSrcsReady()
 236 {
 237     // For now I am assuming that src registers 1..n-1 are the ones that the
 238     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 239     // stored)
 240
 241     for (int i = 1; i < numSrcRegs(); ++i) {
 242         if (!_readySrcRegIdx[i])
 243             return false;
 244     }
 245
 246     return true;
 247 }