src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_BASE_DYN_INST_IMPL_HH__
  44 #define __CPU_BASE_DYN_INST_IMPL_HH__
  45
  46 #include <iostream>
  47 #include <set>
  48 #include <sstream>
  49 #include <string>
  50
  51 #include "base/cprintf.hh"
  52 #include "base/trace.hh"
  53 #include "config/the_isa.hh"
  54 #include "cpu/base_dyn_inst.hh"
  55 #include "cpu/exetrace.hh"
  56 #include "debug/DynInst.hh"
  57 #include "debug/IQ.hh"
  58 #include "mem/request.hh"
  59 #include "sim/faults.hh"
  60
  61 template <class Impl>
  62 BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
  63                                const StaticInstPtr &_macroop,
  64                                TheISA::PCState _pc, TheISA::PCState _predPC,
  65                                InstSeqNum seq_num, ImplCPU *cpu)
  66   : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
  67 {
  68     seqNum = seq_num;
  69
  70     pc = _pc;
  71     predPC = _predPC;
  72
  73     initVars();
  74 }
  75
  76 template <class Impl>
  77 BaseDynInst<Impl>::BaseDynInst(const StaticInstPtr &_staticInst,
  78                                const StaticInstPtr &_macroop)
  79     : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
  80 {
  81     seqNum = 0;
  82     initVars();
  83 }
  84
  85 template <class Impl>
  86 void
  87 BaseDynInst<Impl>::initVars()
  88 {
  89     memData = NULL;
  90     effAddr = 0;
  91     physEffAddr = 0;
  92     readyRegs = 0;
  93     memReqFlags = 0;
  94
  95     status.reset();
  96
  97     instFlags.reset();
  98     instFlags[RecordResult] = true;
  99     instFlags[Predicate] = true;
 100
 101     lqIdx = -1;
 102     sqIdx = -1;
 103
 104     // Eventually make this a parameter.
 105     threadNumber = 0;
 106
 107     // Also make this a parameter, or perhaps get it from xc or cpu.
 108     asid = 0;
 109
 110     // Initialize the fault to be NoFault.
 111     fault = NoFault;
 112
 113 #ifndef NDEBUG
 114     ++cpu->instcount;
 115
 116     if (cpu->instcount > 1500) {
 117 #ifdef DEBUG
 118         cpu->dumpInsts();
 119         dumpSNList();
 120 #endif
 121         assert(cpu->instcount <= 1500);
 122     }
 123
 124     DPRINTF(DynInst,
 125         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 126         seqNum, cpu->name(), cpu->instcount);
 127 #endif
 128
 129 #ifdef DEBUG
 130     cpu->snList.insert(seqNum);
 131 #endif
 132
 133     reqToVerify = NULL;
 134 }
 135
 136 template <class Impl>
 137 BaseDynInst<Impl>::~BaseDynInst()
 138 {
 139     if (memData) {
 140         delete [] memData;
 141     }
 142
 143     if (traceData) {
 144         delete traceData;
 145     }
 146
 147     fault = NoFault;
 148
 149 #ifndef NDEBUG
 150     --cpu->instcount;
 151
 152     DPRINTF(DynInst,
 153         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 154         seqNum, cpu->name(), cpu->instcount);
 155 #endif
 156 #ifdef DEBUG
 157     cpu->snList.erase(seqNum);
 158 #endif
 159
 160     if (reqToVerify)
 161         delete reqToVerify;
 162 }
 163
 164 #ifdef DEBUG
 165 template <class Impl>
 166 void
 167 BaseDynInst<Impl>::dumpSNList()
 168 {
 169     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 170
 171     int count = 0;
 172     while (sn_it != cpu->snList.end()) {
 173         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 174         count++;
 175         sn_it++;
 176     }
 177 }
 178 #endif
 179
 180 template <class Impl>
 181 void
 182 BaseDynInst<Impl>::dump()
 183 {
 184     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 185     std::cout << staticInst->disassemble(pc.instAddr());
 186     cprintf("'\n");
 187 }
 188
 189 template <class Impl>
 190 void
 191 BaseDynInst<Impl>::dump(std::string &outstring)
 192 {
 193     std::ostringstream s;
 194     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 195       << staticInst->disassemble(pc.instAddr());
 196
 197     outstring = s.str();
 198 }
 199
 200 template <class Impl>
 201 void
 202 BaseDynInst<Impl>::markSrcRegReady()
 203 {
 204     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 205             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 206     if (++readyRegs == numSrcRegs()) {
 207         setCanIssue();
 208     }
 209 }
 210
 211 template <class Impl>
 212 void
 213 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 214 {
 215     _readySrcRegIdx[src_idx] = true;
 216
 217     markSrcRegReady();
 218 }
 219
 220 template <class Impl>
 221 bool
 222 BaseDynInst<Impl>::eaSrcsReady()
 223 {
 224     // For now I am assuming that src registers 1..n-1 are the ones that the
 225     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 226     // stored)
 227
 228     for (int i = 1; i < numSrcRegs(); ++i) {
 229         if (!_readySrcRegIdx[i])
 230             return false;
 231     }
 232
 233     return true;
 234 }
 235
 236 #endif//__CPU_BASE_DYN_INST_IMPL_HH__