src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #ifndef __CPU_BASE_DYN_INST_IMPL_HH__
  44 #define __CPU_BASE_DYN_INST_IMPL_HH__
  45
  46 #include <iostream>
  47 #include <set>
  48 #include <sstream>
  49 #include <string>
  50
  51 #include "base/cprintf.hh"
  52 #include "base/trace.hh"
  53 #include "config/the_isa.hh"
  54 #include "cpu/base_dyn_inst.hh"
  55 #include "cpu/exetrace.hh"
  56 #include "debug/DynInst.hh"
  57 #include "debug/IQ.hh"
  58 #include "mem/request.hh"
  59 #include "sim/faults.hh"
  60
  61 template <class Impl>
  62 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  63                                StaticInstPtr _macroop,
  64                                TheISA::PCState _pc, TheISA::PCState _predPC,
  65                                InstSeqNum seq_num, ImplCPU *cpu)
  66   : staticInst(_staticInst), cpu(cpu), traceData(NULL), macroop(_macroop)
  67 {
  68     seqNum = seq_num;
  69
  70     pc = _pc;
  71     predPC = _predPC;
  72
  73     initVars();
  74 }
  75
  76 template <class Impl>
  77 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  78                                StaticInstPtr _macroop)
  79     : staticInst(_staticInst), traceData(NULL), macroop(_macroop)
  80 {
  81     seqNum = 0;
  82     initVars();
  83 }
  84
  85 template <class Impl>
  86 void
  87 BaseDynInst<Impl>::initVars()
  88 {
  89     memData = NULL;
  90     effAddr = 0;
  91     physEffAddr = 0;
  92     readyRegs = 0;
  93
  94     status.reset();
  95
  96     instFlags.reset();
  97     instFlags[RecordResult] = true;
  98     instFlags[Predicate] = true;
  99
 100     lqIdx = -1;
 101     sqIdx = -1;
 102
 103     // Eventually make this a parameter.
 104     threadNumber = 0;
 105
 106     // Also make this a parameter, or perhaps get it from xc or cpu.
 107     asid = 0;
 108
 109     // Initialize the fault to be NoFault.
 110     fault = NoFault;
 111
 112 #ifndef NDEBUG
 113     ++cpu->instcount;
 114
 115     if (cpu->instcount > 1500) {
 116 #ifdef DEBUG
 117         cpu->dumpInsts();
 118         dumpSNList();
 119 #endif
 120         assert(cpu->instcount <= 1500);
 121     }
 122
 123     DPRINTF(DynInst,
 124         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 125         seqNum, cpu->name(), cpu->instcount);
 126 #endif
 127
 128 #ifdef DEBUG
 129     cpu->snList.insert(seqNum);
 130 #endif
 131
 132     reqToVerify = NULL;
 133 }
 134
 135 template <class Impl>
 136 BaseDynInst<Impl>::~BaseDynInst()
 137 {
 138     if (memData) {
 139         delete [] memData;
 140     }
 141
 142     if (traceData) {
 143         delete traceData;
 144     }
 145
 146     fault = NoFault;
 147
 148 #ifndef NDEBUG
 149     --cpu->instcount;
 150
 151     DPRINTF(DynInst,
 152         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 153         seqNum, cpu->name(), cpu->instcount);
 154 #endif
 155 #ifdef DEBUG
 156     cpu->snList.erase(seqNum);
 157 #endif
 158
 159     if (reqToVerify)
 160         delete reqToVerify;
 161 }
 162
 163 #ifdef DEBUG
 164 template <class Impl>
 165 void
 166 BaseDynInst<Impl>::dumpSNList()
 167 {
 168     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 169
 170     int count = 0;
 171     while (sn_it != cpu->snList.end()) {
 172         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 173         count++;
 174         sn_it++;
 175     }
 176 }
 177 #endif
 178
 179 template <class Impl>
 180 void
 181 BaseDynInst<Impl>::dump()
 182 {
 183     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 184     std::cout << staticInst->disassemble(pc.instAddr());
 185     cprintf("'\n");
 186 }
 187
 188 template <class Impl>
 189 void
 190 BaseDynInst<Impl>::dump(std::string &outstring)
 191 {
 192     std::ostringstream s;
 193     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 194       << staticInst->disassemble(pc.instAddr());
 195
 196     outstring = s.str();
 197 }
 198
 199 template <class Impl>
 200 void
 201 BaseDynInst<Impl>::markSrcRegReady()
 202 {
 203     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 204             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 205     if (++readyRegs == numSrcRegs()) {
 206         setCanIssue();
 207     }
 208 }
 209
 210 template <class Impl>
 211 void
 212 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 213 {
 214     _readySrcRegIdx[src_idx] = true;
 215
 216     markSrcRegReady();
 217 }
 218
 219 template <class Impl>
 220 bool
 221 BaseDynInst<Impl>::eaSrcsReady()
 222 {
 223     // For now I am assuming that src registers 1..n-1 are the ones that the
 224     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 225     // stored)
 226
 227     for (int i = 1; i < numSrcRegs(); ++i) {
 228         if (!_readySrcRegIdx[i])
 229             return false;
 230     }
 231
 232     return true;
 233 }
 234
 235 #endif//__CPU_BASE_DYN_INST_IMPL_HH__