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36 #include "base/cprintf.hh"
37 #include "base/trace.hh"
39 #include "sim/faults.hh"
40 #include "cpu/exetrace.hh"
41 #include "mem/request.hh"
43 #include "cpu/base_dyn_inst.hh"
48 #include "base/hashmap.hh"
50 unsigned int MyHashFunc(const BaseDynInst *addr)
52 unsigned a = (unsigned)addr;
53 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
58 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
65 BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
66 Addr pred_PC, InstSeqNum seq_num,
68 : staticInst(machInst), traceData(NULL), cpu(cpu)
73 nextPC = PC + sizeof(TheISA::MachInst);
74 nextNPC = nextPC + sizeof(TheISA::MachInst);
81 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
82 : staticInst(_staticInst), traceData(NULL)
90 BaseDynInst<Impl>::initVars()
99 instResult.integer = 0;
109 // Eventually make this a parameter.
112 // Also make this a parameter, or perhaps get it from xc or cpu.
115 // Initialize the fault to be NoFault.
120 if (instcount > 1500) {
125 assert(instcount <= 1500);
128 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
132 cpu->snList.insert(seqNum);
136 template <class Impl>
137 BaseDynInst<Impl>::~BaseDynInst()
155 DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
158 cpu->snList.erase(seqNum);
163 template <class Impl>
165 BaseDynInst<Impl>::dumpSNList()
167 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
170 while (sn_it != cpu->snList.end()) {
171 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
178 template <class Impl>
180 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
182 // This is the "functional" implementation of prefetch. Not much
183 // happens here since prefetches don't affect the architectural
186 // Generate a MemReq so we can translate the effective address.
187 MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
190 // Prefetches never cause faults.
193 // note this is a local, not BaseDynInst::fault
194 Fault trans_fault = cpu->translateDataReadReq(req);
196 if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
197 // It's a valid address to cacheable space. Record key MemReq
198 // parameters so we can generate another one just like it for
199 // the timing access without calling translate() again (which
200 // might mess up the TLB).
201 effAddr = req->vaddr;
202 physEffAddr = req->paddr;
203 memReqFlags = req->flags;
205 // Bogus address (invalid or uncacheable space). Mark it by
206 // setting the eff_addr to InvalidAddr.
207 effAddr = physEffAddr = MemReq::inval_addr;
211 traceData->setAddr(addr);
216 template <class Impl>
218 BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
220 // Not currently supported.
224 * @todo Need to find a way to get the cache block size here.
226 template <class Impl>
228 BaseDynInst<Impl>::copySrcTranslate(Addr src)
230 // Not currently supported.
235 * @todo Need to find a way to get the cache block size here.
237 template <class Impl>
239 BaseDynInst<Impl>::copy(Addr dest)
241 // Not currently supported.
245 template <class Impl>
247 BaseDynInst<Impl>::dump()
249 cprintf("T%d : %#08d `", threadNumber, PC);
250 std::cout << staticInst->disassemble(PC);
254 template <class Impl>
256 BaseDynInst<Impl>::dump(std::string &outstring)
258 std::ostringstream s;
259 s << "T" << threadNumber << " : 0x" << PC << " "
260 << staticInst->disassemble(PC);
265 template <class Impl>
267 BaseDynInst<Impl>::markSrcRegReady()
269 if (++readyRegs == numSrcRegs()) {
270 status.set(CanIssue);
274 template <class Impl>
276 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
278 _readySrcRegIdx[src_idx] = true;
283 template <class Impl>
285 BaseDynInst<Impl>::eaSrcsReady()
287 // For now I am assuming that src registers 1..n-1 are the ones that the
288 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
291 for (int i = 1; i < numSrcRegs(); ++i) {
292 if (!_readySrcRegIdx[i])