src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #include <iostream>
  44 #include <set>
  45 #include <sstream>
  46 #include <string>
  47
  48 #include "base/cprintf.hh"
  49 #include "base/trace.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base_dyn_inst.hh"
  52 #include "cpu/exetrace.hh"
  53 #include "debug/DynInst.hh"
  54 #include "debug/IQ.hh"
  55 #include "mem/request.hh"
  56 #include "sim/faults.hh"
  57
  58 template <class Impl>
  59 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  60                                StaticInstPtr _macroop,
  61                                TheISA::PCState _pc, TheISA::PCState _predPC,
  62                                InstSeqNum seq_num, ImplCPU *cpu)
  63   : staticInst(_staticInst), macroop(_macroop), traceData(NULL), cpu(cpu)
  64 {
  65     seqNum = seq_num;
  66
  67     pc = _pc;
  68     predPC = _predPC;
  69     predTaken = false;
  70
  71     initVars();
  72 }
  73
  74 template <class Impl>
  75 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  76                                StaticInstPtr _macroop)
  77     : staticInst(_staticInst), macroop(_macroop), traceData(NULL)
  78 {
  79     seqNum = 0;
  80     initVars();
  81 }
  82
  83 template <class Impl>
  84 void
  85 BaseDynInst<Impl>::initVars()
  86 {
  87     memData = NULL;
  88     effAddr = 0;
  89     effAddrValid = false;
  90     physEffAddr = 0;
  91
  92     translationStarted = false;
  93     translationCompleted = false;
  94     possibleLoadViolation = false;
  95     hitExternalSnoop  = false;
  96
  97     isUncacheable = false;
  98     reqMade = false;
  99     readyRegs = 0;
 100
 101     recordResult = true;
 102
 103     status.reset();
 104
 105     eaCalcDone = false;
 106     memOpDone = false;
 107     predicate = true;
 108
 109     lqIdx = -1;
 110     sqIdx = -1;
 111
 112     // Eventually make this a parameter.
 113     threadNumber = 0;
 114
 115     // Also make this a parameter, or perhaps get it from xc or cpu.
 116     asid = 0;
 117
 118     // Initialize the fault to be NoFault.
 119     fault = NoFault;
 120
 121 #ifndef NDEBUG
 122     ++cpu->instcount;
 123
 124     if (cpu->instcount > 1500) {
 125 #ifdef DEBUG
 126         cpu->dumpInsts();
 127         dumpSNList();
 128 #endif
 129         assert(cpu->instcount <= 1500);
 130     }
 131
 132     DPRINTF(DynInst,
 133         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 134         seqNum, cpu->name(), cpu->instcount);
 135 #endif
 136
 137 #ifdef DEBUG
 138     cpu->snList.insert(seqNum);
 139 #endif
 140
 141     reqToVerify = NULL;
 142 }
 143
 144 template <class Impl>
 145 BaseDynInst<Impl>::~BaseDynInst()
 146 {
 147     if (memData) {
 148         delete [] memData;
 149     }
 150
 151     if (traceData) {
 152         delete traceData;
 153     }
 154
 155     fault = NoFault;
 156
 157 #ifndef NDEBUG
 158     --cpu->instcount;
 159
 160     DPRINTF(DynInst,
 161         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 162         seqNum, cpu->name(), cpu->instcount);
 163 #endif
 164 #ifdef DEBUG
 165     cpu->snList.erase(seqNum);
 166 #endif
 167
 168     if (reqToVerify)
 169         delete reqToVerify;
 170 }
 171
 172 #ifdef DEBUG
 173 template <class Impl>
 174 void
 175 BaseDynInst<Impl>::dumpSNList()
 176 {
 177     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 178
 179     int count = 0;
 180     while (sn_it != cpu->snList.end()) {
 181         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 182         count++;
 183         sn_it++;
 184     }
 185 }
 186 #endif
 187
 188 template <class Impl>
 189 void
 190 BaseDynInst<Impl>::dump()
 191 {
 192     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 193     std::cout << staticInst->disassemble(pc.instAddr());
 194     cprintf("'\n");
 195 }
 196
 197 template <class Impl>
 198 void
 199 BaseDynInst<Impl>::dump(std::string &outstring)
 200 {
 201     std::ostringstream s;
 202     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 203       << staticInst->disassemble(pc.instAddr());
 204
 205     outstring = s.str();
 206 }
 207
 208 template <class Impl>
 209 void
 210 BaseDynInst<Impl>::markSrcRegReady()
 211 {
 212     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 213             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 214     if (++readyRegs == numSrcRegs()) {
 215         setCanIssue();
 216     }
 217 }
 218
 219 template <class Impl>
 220 void
 221 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 222 {
 223     _readySrcRegIdx[src_idx] = true;
 224
 225     markSrcRegReady();
 226 }
 227
 228 template <class Impl>
 229 bool
 230 BaseDynInst<Impl>::eaSrcsReady()
 231 {
 232     // For now I am assuming that src registers 1..n-1 are the ones that the
 233     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 234     // stored)
 235
 236     for (int i = 1; i < numSrcRegs(); ++i) {
 237         if (!_readySrcRegIdx[i])
 238             return false;
 239     }
 240
 241     return true;
 242 }