src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <iostream>
  32 #include <set>
  33 #include <string>
  34 #include <sstream>
  35
  36 #include "base/cprintf.hh"
  37 #include "base/trace.hh"
  38
  39 #include "arch/faults.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "mem/request.hh"
  42
  43 #include "cpu/base_dyn_inst.hh"
  44
  45 using namespace std;
  46 using namespace TheISA;
  47
  48 #define NOHASH
  49 #ifndef NOHASH
  50
  51 #include "base/hashmap.hh"
  52
  53 unsigned int MyHashFunc(const BaseDynInst *addr)
  54 {
  55     unsigned a = (unsigned)addr;
  56     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
  57
  58     return hash;
  59 }
  60
  61 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
  62 my_hash_t;
  63
  64 my_hash_t thishash;
  65 #endif
  66
  67 template <class Impl>
  68 BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
  69                                Addr pred_PC, InstSeqNum seq_num,
  70                                ImplCPU *cpu)
  71   : staticInst(machInst), traceData(NULL), cpu(cpu)
  72 {
  73     seqNum = seq_num;
  74
  75     PC = inst_PC;
  76     nextPC = PC + sizeof(MachInst);
  77     nextNPC = nextPC + sizeof(MachInst);
  78     predPC = pred_PC;
  79
  80     initVars();
  81 }
  82
  83 template <class Impl>
  84 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
  85     : staticInst(_staticInst), traceData(NULL)
  86 {
  87     seqNum = 0;
  88     initVars();
  89 }
  90
  91 template <class Impl>
  92 void
  93 BaseDynInst<Impl>::initVars()
  94 {
  95     req = NULL;
  96     memData = NULL;
  97     effAddr = 0;
  98     physEffAddr = 0;
  99
 100     readyRegs = 0;
 101
 102     instResult.integer = 0;
 103
 104     status.reset();
 105
 106     eaCalcDone = false;
 107     memOpDone = false;
 108
 109     lqIdx = -1;
 110     sqIdx = -1;
 111
 112     // Eventually make this a parameter.
 113     threadNumber = 0;
 114
 115     // Also make this a parameter, or perhaps get it from xc or cpu.
 116     asid = 0;
 117
 118     // Initialize the fault to be NoFault.
 119     fault = NoFault;
 120
 121     ++instcount;
 122
 123     if (instcount > 1500) {
 124         cpu->dumpInsts();
 125 #ifdef DEBUG
 126         dumpSNList();
 127 #endif
 128         assert(instcount <= 1500);
 129     }
 130
 131     DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction created. Instcount=%i\n",
 132             seqNum, instcount);
 133
 134 #ifdef DEBUG
 135     cpu->snList.insert(seqNum);
 136 #endif
 137 }
 138
 139 template <class Impl>
 140 BaseDynInst<Impl>::~BaseDynInst()
 141 {
 142     if (req) {
 143         delete req;
 144     }
 145
 146     if (memData) {
 147         delete [] memData;
 148     }
 149
 150     if (traceData) {
 151         delete traceData;
 152     }
 153
 154     fault = NoFault;
 155
 156     --instcount;
 157
 158     DPRINTF(DynInst, "DynInst: [sn:%lli] Instruction destroyed. Instcount=%i\n",
 159             seqNum, instcount);
 160 #ifdef DEBUG
 161     cpu->snList.erase(seqNum);
 162 #endif
 163 }
 164
 165 #ifdef DEBUG
 166 template <class Impl>
 167 void
 168 BaseDynInst<Impl>::dumpSNList()
 169 {
 170     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 171
 172     int count = 0;
 173     while (sn_it != cpu->snList.end()) {
 174         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 175         count++;
 176         sn_it++;
 177     }
 178 }
 179 #endif
 180
 181 template <class Impl>
 182 void
 183 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
 184 {
 185     // This is the "functional" implementation of prefetch.  Not much
 186     // happens here since prefetches don't affect the architectural
 187     // state.
 188 /*
 189     // Generate a MemReq so we can translate the effective address.
 190     MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
 191     req->asid = asid;
 192
 193     // Prefetches never cause faults.
 194     fault = NoFault;
 195
 196     // note this is a local, not BaseDynInst::fault
 197     Fault trans_fault = cpu->translateDataReadReq(req);
 198
 199     if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
 200         // It's a valid address to cacheable space.  Record key MemReq
 201         // parameters so we can generate another one just like it for
 202         // the timing access without calling translate() again (which
 203         // might mess up the TLB).
 204         effAddr = req->vaddr;
 205         physEffAddr = req->paddr;
 206         memReqFlags = req->flags;
 207     } else {
 208         // Bogus address (invalid or uncacheable space).  Mark it by
 209         // setting the eff_addr to InvalidAddr.
 210         effAddr = physEffAddr = MemReq::inval_addr;
 211     }
 212
 213     if (traceData) {
 214         traceData->setAddr(addr);
 215     }
 216 */
 217 }
 218
 219 template <class Impl>
 220 void
 221 BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 222 {
 223     // Not currently supported.
 224 }
 225
 226 /**
 227  * @todo Need to find a way to get the cache block size here.
 228  */
 229 template <class Impl>
 230 Fault
 231 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 232 {
 233     // Not currently supported.
 234     return NoFault;
 235 }
 236
 237 /**
 238  * @todo Need to find a way to get the cache block size here.
 239  */
 240 template <class Impl>
 241 Fault
 242 BaseDynInst<Impl>::copy(Addr dest)
 243 {
 244     // Not currently supported.
 245     return NoFault;
 246 }
 247
 248 template <class Impl>
 249 void
 250 BaseDynInst<Impl>::dump()
 251 {
 252     cprintf("T%d : %#08d `", threadNumber, PC);
 253     cout << staticInst->disassemble(PC);
 254     cprintf("'\n");
 255 }
 256
 257 template <class Impl>
 258 void
 259 BaseDynInst<Impl>::dump(std::string &outstring)
 260 {
 261     std::ostringstream s;
 262     s << "T" << threadNumber << " : 0x" << PC << " "
 263       << staticInst->disassemble(PC);
 264
 265     outstring = s.str();
 266 }
 267
 268 template <class Impl>
 269 void
 270 BaseDynInst<Impl>::markSrcRegReady()
 271 {
 272     if (++readyRegs == numSrcRegs()) {
 273         status.set(CanIssue);
 274     }
 275 }
 276
 277 template <class Impl>
 278 void
 279 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 280 {
 281     _readySrcRegIdx[src_idx] = true;
 282
 283     markSrcRegReady();
 284 }
 285
 286 template <class Impl>
 287 bool
 288 BaseDynInst<Impl>::eaSrcsReady()
 289 {
 290     // For now I am assuming that src registers 1..n-1 are the ones that the
 291     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 292     // stored)
 293
 294     for (int i = 1; i < numSrcRegs(); ++i) {
 295         if (!_readySrcRegIdx[i])
 296             return false;
 297     }
 298
 299     return true;
 300 }