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48 #include "base/cprintf.hh"
49 #include "base/trace.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/base_dyn_inst.hh"
52 #include "cpu/exetrace.hh"
53 #include "debug/DynInst.hh"
54 #include "debug/IQ.hh"
55 #include "mem/request.hh"
56 #include "sim/faults.hh"
61 #include "base/hashmap.hh"
63 unsigned int MyHashFunc(const BaseDynInst *addr)
65 unsigned a = (unsigned)addr;
66 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
71 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
78 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
79 TheISA::PCState _pc, TheISA::PCState _predPC,
80 InstSeqNum seq_num, ImplCPU *cpu)
81 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
93 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
94 : staticInst(_staticInst), traceData(NULL)
100 template <class Impl>
102 BaseDynInst<Impl>::initVars()
106 effAddrValid = false;
109 translationStarted = false;
110 translationCompleted = false;
112 isUncacheable = false;
116 instResult.integer = 0;
128 // Eventually make this a parameter.
131 // Also make this a parameter, or perhaps get it from xc or cpu.
134 // Initialize the fault to be NoFault.
140 if (cpu->instcount > 1500) {
145 assert(cpu->instcount <= 1500);
149 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
150 seqNum, cpu->name(), cpu->instcount);
154 cpu->snList.insert(seqNum);
158 template <class Impl>
159 BaseDynInst<Impl>::~BaseDynInst()
175 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
176 seqNum, cpu->name(), cpu->instcount);
179 cpu->snList.erase(seqNum);
184 template <class Impl>
186 BaseDynInst<Impl>::dumpSNList()
188 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
191 while (sn_it != cpu->snList.end()) {
192 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
199 template <class Impl>
201 BaseDynInst<Impl>::dump()
203 cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
204 std::cout << staticInst->disassemble(pc.instAddr());
208 template <class Impl>
210 BaseDynInst<Impl>::dump(std::string &outstring)
212 std::ostringstream s;
213 s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
214 << staticInst->disassemble(pc.instAddr());
219 template <class Impl>
221 BaseDynInst<Impl>::markSrcRegReady()
223 DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
224 seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
225 if (++readyRegs == numSrcRegs()) {
230 template <class Impl>
232 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
234 _readySrcRegIdx[src_idx] = true;
239 template <class Impl>
241 BaseDynInst<Impl>::eaSrcsReady()
243 // For now I am assuming that src registers 1..n-1 are the ones that the
244 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
247 for (int i = 1; i < numSrcRegs(); ++i) {
248 if (!_readySrcRegIdx[i])