src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include <iostream>
  32 #include <set>
  33 #include <string>
  34 #include <sstream>
  35
  36 #include "base/cprintf.hh"
  37 #include "base/trace.hh"
  38 #include "config/the_isa.hh"
  39 #include "cpu/base_dyn_inst.hh"
  40 #include "cpu/exetrace.hh"
  41 #include "mem/request.hh"
  42 #include "sim/faults.hh"
  43
  44 #define NOHASH
  45 #ifndef NOHASH
  46
  47 #include "base/hashmap.hh"
  48
  49 unsigned int MyHashFunc(const BaseDynInst *addr)
  50 {
  51     unsigned a = (unsigned)addr;
  52     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
  53
  54     return hash;
  55 }
  56
  57 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
  58 my_hash_t;
  59
  60 my_hash_t thishash;
  61 #endif
  62
  63 template <class Impl>
  64 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  65                                TheISA::PCState _pc, TheISA::PCState _predPC,
  66                                InstSeqNum seq_num, ImplCPU *cpu)
  67   : staticInst(_staticInst), traceData(NULL), cpu(cpu)
  68 {
  69     seqNum = seq_num;
  70
  71     pc = _pc;
  72     predPC = _predPC;
  73     predTaken = false;
  74
  75     initVars();
  76 }
  77
  78 template <class Impl>
  79 BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
  80                                TheISA::PCState _pc, TheISA::PCState _predPC,
  81                                InstSeqNum seq_num, ImplCPU *cpu)
  82   : staticInst(inst, _pc.instAddr()), traceData(NULL), cpu(cpu)
  83 {
  84     seqNum = seq_num;
  85
  86     pc = _pc;
  87     predPC = _predPC;
  88     predTaken = false;
  89
  90     initVars();
  91 }
  92
  93 template <class Impl>
  94 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
  95     : staticInst(_staticInst), traceData(NULL)
  96 {
  97     seqNum = 0;
  98     initVars();
  99 }
 100
 101 template <class Impl>
 102 void
 103 BaseDynInst<Impl>::initVars()
 104 {
 105     memData = NULL;
 106     effAddr = 0;
 107     effAddrValid = false;
 108     physEffAddr = 0;
 109
 110     isUncacheable = false;
 111     reqMade = false;
 112     readyRegs = 0;
 113
 114     instResult.integer = 0;
 115     recordResult = true;
 116
 117     status.reset();
 118
 119     eaCalcDone = false;
 120     memOpDone = false;
 121     predicate = true;
 122
 123     lqIdx = -1;
 124     sqIdx = -1;
 125
 126     // Eventually make this a parameter.
 127     threadNumber = 0;
 128
 129     // Also make this a parameter, or perhaps get it from xc or cpu.
 130     asid = 0;
 131
 132     // Initialize the fault to be NoFault.
 133     fault = NoFault;
 134
 135 #ifndef NDEBUG
 136     ++cpu->instcount;
 137
 138     if (cpu->instcount > 1500) {
 139 #ifdef DEBUG
 140         cpu->dumpInsts();
 141         dumpSNList();
 142 #endif
 143         assert(cpu->instcount <= 1500);
 144     }
 145
 146     DPRINTF(DynInst,
 147         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 148         seqNum, cpu->name(), cpu->instcount);
 149 #endif
 150
 151 #ifdef DEBUG
 152     cpu->snList.insert(seqNum);
 153 #endif
 154 }
 155
 156 template <class Impl>
 157 BaseDynInst<Impl>::~BaseDynInst()
 158 {
 159     if (memData) {
 160         delete [] memData;
 161     }
 162
 163     if (traceData) {
 164         delete traceData;
 165     }
 166
 167     fault = NoFault;
 168
 169 #ifndef NDEBUG
 170     --cpu->instcount;
 171
 172     DPRINTF(DynInst,
 173         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 174         seqNum, cpu->name(), cpu->instcount);
 175 #endif
 176 #ifdef DEBUG
 177     cpu->snList.erase(seqNum);
 178 #endif
 179 }
 180
 181 #ifdef DEBUG
 182 template <class Impl>
 183 void
 184 BaseDynInst<Impl>::dumpSNList()
 185 {
 186     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 187
 188     int count = 0;
 189     while (sn_it != cpu->snList.end()) {
 190         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 191         count++;
 192         sn_it++;
 193     }
 194 }
 195 #endif
 196
 197 template <class Impl>
 198 void
 199 BaseDynInst<Impl>::prefetch(Addr addr, unsigned flags)
 200 {
 201     // This is the "functional" implementation of prefetch.  Not much
 202     // happens here since prefetches don't affect the architectural
 203     // state.
 204 /*
 205     // Generate a MemReq so we can translate the effective address.
 206     MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
 207     req->asid = asid;
 208
 209     // Prefetches never cause faults.
 210     fault = NoFault;
 211
 212     // note this is a local, not BaseDynInst::fault
 213     Fault trans_fault = cpu->translateDataReadReq(req);
 214
 215     if (trans_fault == NoFault && !(req->isUncacheable())) {
 216         // It's a valid address to cacheable space.  Record key MemReq
 217         // parameters so we can generate another one just like it for
 218         // the timing access without calling translate() again (which
 219         // might mess up the TLB).
 220         effAddr = req->vaddr;
 221         physEffAddr = req->paddr;
 222         memReqFlags = req->flags;
 223     } else {
 224         // Bogus address (invalid or uncacheable space).  Mark it by
 225         // setting the eff_addr to InvalidAddr.
 226         effAddr = physEffAddr = MemReq::inval_addr;
 227     }
 228
 229     if (traceData) {
 230         traceData->setAddr(addr);
 231     }
 232 */
 233 }
 234
 235 template <class Impl>
 236 void
 237 BaseDynInst<Impl>::writeHint(Addr addr, int size, unsigned flags)
 238 {
 239     // Not currently supported.
 240 }
 241
 242 /**
 243  * @todo Need to find a way to get the cache block size here.
 244  */
 245 template <class Impl>
 246 Fault
 247 BaseDynInst<Impl>::copySrcTranslate(Addr src)
 248 {
 249     // Not currently supported.
 250     return NoFault;
 251 }
 252
 253 /**
 254  * @todo Need to find a way to get the cache block size here.
 255  */
 256 template <class Impl>
 257 Fault
 258 BaseDynInst<Impl>::copy(Addr dest)
 259 {
 260     // Not currently supported.
 261     return NoFault;
 262 }
 263
 264 template <class Impl>
 265 void
 266 BaseDynInst<Impl>::dump()
 267 {
 268     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 269     std::cout << staticInst->disassemble(pc.instAddr());
 270     cprintf("'\n");
 271 }
 272
 273 template <class Impl>
 274 void
 275 BaseDynInst<Impl>::dump(std::string &outstring)
 276 {
 277     std::ostringstream s;
 278     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 279       << staticInst->disassemble(pc.instAddr());
 280
 281     outstring = s.str();
 282 }
 283
 284 template <class Impl>
 285 void
 286 BaseDynInst<Impl>::markSrcRegReady()
 287 {
 288     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 289             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 290     if (++readyRegs == numSrcRegs()) {
 291         setCanIssue();
 292     }
 293 }
 294
 295 template <class Impl>
 296 void
 297 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 298 {
 299     _readySrcRegIdx[src_idx] = true;
 300
 301     markSrcRegReady();
 302 }
 303
 304 template <class Impl>
 305 bool
 306 BaseDynInst<Impl>::eaSrcsReady()
 307 {
 308     // For now I am assuming that src registers 1..n-1 are the ones that the
 309     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 310     // stored)
 311
 312     for (int i = 1; i < numSrcRegs(); ++i) {
 313         if (!_readySrcRegIdx[i])
 314             return false;
 315     }
 316
 317     return true;
 318 }