src/cpu/base_dyn_inst_impl.hh

   1 /*
   2  * Copyright (c) 2011 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2004-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  */
  42
  43 #include <iostream>
  44 #include <set>
  45 #include <sstream>
  46 #include <string>
  47
  48 #include "base/cprintf.hh"
  49 #include "base/trace.hh"
  50 #include "config/the_isa.hh"
  51 #include "config/use_checker.hh"
  52 #include "cpu/base_dyn_inst.hh"
  53 #include "cpu/exetrace.hh"
  54 #include "debug/DynInst.hh"
  55 #include "debug/IQ.hh"
  56 #include "mem/request.hh"
  57 #include "sim/faults.hh"
  58
  59 #define NOHASH
  60 #ifndef NOHASH
  61
  62 #include "base/hashmap.hh"
  63
  64 unsigned int MyHashFunc(const BaseDynInst *addr)
  65 {
  66     unsigned a = (unsigned)addr;
  67     unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
  68
  69     return hash;
  70 }
  71
  72 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
  73 my_hash_t;
  74
  75 my_hash_t thishash;
  76 #endif
  77
  78 template <class Impl>
  79 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  80                                StaticInstPtr _macroop,
  81                                TheISA::PCState _pc, TheISA::PCState _predPC,
  82                                InstSeqNum seq_num, ImplCPU *cpu)
  83   : staticInst(_staticInst), macroop(_macroop), traceData(NULL), cpu(cpu)
  84 {
  85     seqNum = seq_num;
  86
  87     pc = _pc;
  88     predPC = _predPC;
  89     predTaken = false;
  90
  91     initVars();
  92 }
  93
  94 template <class Impl>
  95 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
  96                                StaticInstPtr _macroop)
  97     : staticInst(_staticInst), macroop(_macroop), traceData(NULL)
  98 {
  99     seqNum = 0;
 100     initVars();
 101 }
 102
 103 template <class Impl>
 104 void
 105 BaseDynInst<Impl>::initVars()
 106 {
 107     memData = NULL;
 108     effAddr = 0;
 109     effAddrValid = false;
 110     physEffAddr = 0;
 111
 112     translationStarted = false;
 113     translationCompleted = false;
 114     possibleLoadViolation = false;
 115     hitExternalSnoop  = false;
 116
 117     isUncacheable = false;
 118     reqMade = false;
 119     readyRegs = 0;
 120
 121     recordResult = true;
 122
 123     status.reset();
 124
 125     eaCalcDone = false;
 126     memOpDone = false;
 127     predicate = true;
 128
 129     lqIdx = -1;
 130     sqIdx = -1;
 131
 132     // Eventually make this a parameter.
 133     threadNumber = 0;
 134
 135     // Also make this a parameter, or perhaps get it from xc or cpu.
 136     asid = 0;
 137
 138     // Initialize the fault to be NoFault.
 139     fault = NoFault;
 140
 141 #ifndef NDEBUG
 142     ++cpu->instcount;
 143
 144     if (cpu->instcount > 1500) {
 145 #ifdef DEBUG
 146         cpu->dumpInsts();
 147         dumpSNList();
 148 #endif
 149         assert(cpu->instcount <= 1500);
 150     }
 151
 152     DPRINTF(DynInst,
 153         "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
 154         seqNum, cpu->name(), cpu->instcount);
 155 #endif
 156
 157 #ifdef DEBUG
 158     cpu->snList.insert(seqNum);
 159 #endif
 160
 161 #if USE_CHECKER
 162     reqToVerify = NULL;
 163 #endif
 164 }
 165
 166 template <class Impl>
 167 BaseDynInst<Impl>::~BaseDynInst()
 168 {
 169     if (memData) {
 170         delete [] memData;
 171     }
 172
 173     if (traceData) {
 174         delete traceData;
 175     }
 176
 177     fault = NoFault;
 178
 179 #ifndef NDEBUG
 180     --cpu->instcount;
 181
 182     DPRINTF(DynInst,
 183         "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
 184         seqNum, cpu->name(), cpu->instcount);
 185 #endif
 186 #ifdef DEBUG
 187     cpu->snList.erase(seqNum);
 188 #endif
 189
 190 #if USE_CHECKER
 191     if (reqToVerify)
 192         delete reqToVerify;
 193 #endif // USE_CHECKER
 194 }
 195
 196 #ifdef DEBUG
 197 template <class Impl>
 198 void
 199 BaseDynInst<Impl>::dumpSNList()
 200 {
 201     std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
 202
 203     int count = 0;
 204     while (sn_it != cpu->snList.end()) {
 205         cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
 206         count++;
 207         sn_it++;
 208     }
 209 }
 210 #endif
 211
 212 template <class Impl>
 213 void
 214 BaseDynInst<Impl>::dump()
 215 {
 216     cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
 217     std::cout << staticInst->disassemble(pc.instAddr());
 218     cprintf("'\n");
 219 }
 220
 221 template <class Impl>
 222 void
 223 BaseDynInst<Impl>::dump(std::string &outstring)
 224 {
 225     std::ostringstream s;
 226     s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
 227       << staticInst->disassemble(pc.instAddr());
 228
 229     outstring = s.str();
 230 }
 231
 232 template <class Impl>
 233 void
 234 BaseDynInst<Impl>::markSrcRegReady()
 235 {
 236     DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
 237             seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
 238     if (++readyRegs == numSrcRegs()) {
 239         setCanIssue();
 240     }
 241 }
 242
 243 template <class Impl>
 244 void
 245 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
 246 {
 247     _readySrcRegIdx[src_idx] = true;
 248
 249     markSrcRegReady();
 250 }
 251
 252 template <class Impl>
 253 bool
 254 BaseDynInst<Impl>::eaSrcsReady()
 255 {
 256     // For now I am assuming that src registers 1..n-1 are the ones that the
 257     // EA calc depends on.  (i.e. src reg 0 is the source of the data to be
 258     // stored)
 259
 260     for (int i = 1; i < numSrcRegs(); ++i) {
 261         if (!_readySrcRegIdx[i])
 262             return false;
 263     }
 264
 265     return true;
 266 }