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48 #include "base/cprintf.hh"
49 #include "base/trace.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/base_dyn_inst.hh"
52 #include "cpu/exetrace.hh"
53 #include "mem/request.hh"
54 #include "sim/faults.hh"
59 #include "base/hashmap.hh"
61 unsigned int MyHashFunc(const BaseDynInst *addr)
63 unsigned a = (unsigned)addr;
64 unsigned hash = (((a >> 14) ^ ((a >> 2) & 0xffff))) & 0x7FFFFFFF;
69 typedef m5::hash_map<const BaseDynInst *, const BaseDynInst *, MyHashFunc>
76 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr _staticInst,
77 TheISA::PCState _pc, TheISA::PCState _predPC,
78 InstSeqNum seq_num, ImplCPU *cpu)
79 : staticInst(_staticInst), traceData(NULL), cpu(cpu)
91 BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst inst,
92 TheISA::PCState _pc, TheISA::PCState _predPC,
93 InstSeqNum seq_num, ImplCPU *cpu)
94 : staticInst(inst, _pc.instAddr()), traceData(NULL), cpu(cpu)
105 template <class Impl>
106 BaseDynInst<Impl>::BaseDynInst(StaticInstPtr &_staticInst)
107 : staticInst(_staticInst), traceData(NULL)
113 template <class Impl>
115 BaseDynInst<Impl>::initVars()
119 effAddrValid = false;
122 translationStarted = false;
123 translationCompleted = false;
125 isUncacheable = false;
129 instResult.integer = 0;
141 // Eventually make this a parameter.
144 // Also make this a parameter, or perhaps get it from xc or cpu.
147 // Initialize the fault to be NoFault.
153 if (cpu->instcount > 1500) {
158 assert(cpu->instcount <= 1500);
162 "DynInst: [sn:%lli] Instruction created. Instcount for %s = %i\n",
163 seqNum, cpu->name(), cpu->instcount);
167 cpu->snList.insert(seqNum);
171 template <class Impl>
172 BaseDynInst<Impl>::~BaseDynInst()
188 "DynInst: [sn:%lli] Instruction destroyed. Instcount for %s = %i\n",
189 seqNum, cpu->name(), cpu->instcount);
192 cpu->snList.erase(seqNum);
197 template <class Impl>
199 BaseDynInst<Impl>::dumpSNList()
201 std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
204 while (sn_it != cpu->snList.end()) {
205 cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
212 template <class Impl>
214 BaseDynInst<Impl>::dump()
216 cprintf("T%d : %#08d `", threadNumber, pc.instAddr());
217 std::cout << staticInst->disassemble(pc.instAddr());
221 template <class Impl>
223 BaseDynInst<Impl>::dump(std::string &outstring)
225 std::ostringstream s;
226 s << "T" << threadNumber << " : 0x" << pc.instAddr() << " "
227 << staticInst->disassemble(pc.instAddr());
232 template <class Impl>
234 BaseDynInst<Impl>::markSrcRegReady()
236 DPRINTF(IQ, "[sn:%lli] has %d ready out of %d sources. RTI %d)\n",
237 seqNum, readyRegs+1, numSrcRegs(), readyToIssue());
238 if (++readyRegs == numSrcRegs()) {
243 template <class Impl>
245 BaseDynInst<Impl>::markSrcRegReady(RegIndex src_idx)
247 _readySrcRegIdx[src_idx] = true;
252 template <class Impl>
254 BaseDynInst<Impl>::eaSrcsReady()
256 // For now I am assuming that src registers 1..n-1 are the ones that the
257 // EA calc depends on. (i.e. src reg 0 is the source of the data to be
260 for (int i = 1; i < numSrcRegs(); ++i) {
261 if (!_readySrcRegIdx[i])