2f020c4a94a6c479b86408449dcdea998cab7557
2 * Copyright (c) 2011,2013,2017-2018 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include "cpu/checker/cpu.hh"
49 #include "arch/generic/tlb.hh"
50 #include "arch/vtophys.hh"
51 #include "cpu/base.hh"
52 #include "cpu/simple_thread.hh"
53 #include "cpu/static_inst.hh"
54 #include "cpu/thread_context.hh"
55 #include "cpu/utils.hh"
56 #include "params/CheckerCPU.hh"
57 #include "sim/full_system.hh"
60 using namespace TheISA
;
65 masterId
= systemPtr
->getMasterId(this);
68 CheckerCPU::CheckerCPU(Params
*p
)
69 : BaseCPU(p
, true), systemPtr(NULL
), icachePort(NULL
), dcachePort(NULL
),
70 tc(NULL
), thread(NULL
),
71 unverifiedReq(nullptr),
72 unverifiedMemData(nullptr)
75 curMacroStaticInst
= NULL
;
83 changedPC
= willChangePC
= false;
85 exitOnError
= p
->exitOnError
;
86 warnOnlyOnLoadError
= p
->warnOnlyOnLoadError
;
89 workload
= p
->workload
;
94 CheckerCPU::~CheckerCPU()
99 CheckerCPU::setSystem(System
*system
)
101 const Params
*p(dynamic_cast<const Params
*>(_params
));
106 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
,
109 thread
= new SimpleThread(this, 0, systemPtr
,
110 workload
.size() ? workload
[0] : NULL
,
111 itb
, dtb
, p
->isa
[0]);
114 tc
= thread
->getTC();
115 threadContexts
.push_back(tc
);
116 thread
->kernelStats
= NULL
;
117 // Thread should never be null after this
118 assert(thread
!= NULL
);
122 CheckerCPU::setIcachePort(MasterPort
*icache_port
)
124 icachePort
= icache_port
;
128 CheckerCPU::setDcachePort(MasterPort
*dcache_port
)
130 dcachePort
= dcache_port
;
134 CheckerCPU::serialize(ostream
&os
) const
139 CheckerCPU::unserialize(CheckpointIn
&cp
)
144 CheckerCPU::genMemFragmentRequest(Addr frag_addr
, int size
,
145 Request::Flags flags
,
146 const std::vector
<bool>& byte_enable
,
147 int& frag_size
, int& size_left
) const
149 frag_size
= std::min(
150 cacheLineSize() - addrBlockOffset(frag_addr
, cacheLineSize()),
152 size_left
-= frag_size
;
156 if (!byte_enable
.empty()) {
157 // Set up byte-enable mask for the current fragment
158 auto it_start
= byte_enable
.cbegin() + (size
- (frag_size
+
160 auto it_end
= byte_enable
.cbegin() + (size
- size_left
);
161 if (isAnyActiveElement(it_start
, it_end
)) {
162 mem_req
= std::make_shared
<Request
>(0, frag_addr
, frag_size
,
163 flags
, masterId
, thread
->pcState().instAddr(),
165 mem_req
->setByteEnable(std::vector
<bool>(it_start
, it_end
));
168 mem_req
= std::make_shared
<Request
>(0, frag_addr
, frag_size
,
169 flags
, masterId
, thread
->pcState().instAddr(),
177 CheckerCPU::readMem(Addr addr
, uint8_t *data
, unsigned size
,
178 Request::Flags flags
,
179 const std::vector
<bool>& byte_enable
)
181 assert(byte_enable
.empty() || byte_enable
.size() == size
);
183 Fault fault
= NoFault
;
184 bool checked_flags
= false;
185 bool flags_match
= true;
188 Addr frag_addr
= addr
;
190 int size_left
= size
;
193 // Need to account for multiple accesses like the Atomic and TimingSimple
195 RequestPtr mem_req
= genMemFragmentRequest(frag_addr
, size
, flags
,
196 byte_enable
, frag_size
,
199 predicate
= (mem_req
!= nullptr);
201 // translate to physical address
203 fault
= dtb
->translateFunctional(mem_req
, tc
, BaseTLB::Read
);
206 if (predicate
&& !checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
207 flags_match
= checkFlags(unverifiedReq
, mem_req
->getVaddr(),
208 mem_req
->getPaddr(), mem_req
->getFlags());
209 pAddr
= mem_req
->getPaddr();
210 checked_flags
= true;
214 if (predicate
&& fault
== NoFault
&&
215 !mem_req
->getFlags().isSet(Request::NO_ACCESS
)) {
216 PacketPtr pkt
= Packet::createRead(mem_req
);
218 pkt
->dataStatic(data
);
220 if (!(mem_req
->isUncacheable() || mem_req
->isMmappedIpr())) {
221 // Access memory to see if we have the same data
222 dcachePort
->sendFunctional(pkt
);
224 // Assume the data is correct if it's an uncached access
225 memcpy(data
, unverifiedMemData
, frag_size
);
231 if (fault
!= NoFault
) {
232 if (mem_req
->isPrefetch()) {
238 //If we don't need to access a second cache line, stop now.
244 // Setup for accessing next cache line
245 frag_addr
+= frag_size
;
247 unverifiedMemData
+= frag_size
;
251 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
252 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
253 unverifiedReq
->getFlags(), frag_addr
, pAddr
, flags
);
261 CheckerCPU::writeMem(uint8_t *data
, unsigned size
,
262 Addr addr
, Request::Flags flags
, uint64_t *res
,
263 const std::vector
<bool>& byte_enable
)
265 assert(byte_enable
.empty() || byte_enable
.size() == size
);
267 Fault fault
= NoFault
;
268 bool checked_flags
= false;
269 bool flags_match
= true;
271 static uint8_t zero_data
[64] = {};
273 Addr frag_addr
= addr
;
275 int size_left
= size
;
278 // Need to account for a multiple access like Atomic and Timing CPUs
280 RequestPtr mem_req
= genMemFragmentRequest(frag_addr
, size
, flags
,
281 byte_enable
, frag_size
,
284 predicate
= (mem_req
!= nullptr);
287 fault
= dtb
->translateFunctional(mem_req
, tc
, BaseTLB::Write
);
290 if (predicate
&& !checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
291 flags_match
= checkFlags(unverifiedReq
, mem_req
->getVaddr(),
292 mem_req
->getPaddr(), mem_req
->getFlags());
293 pAddr
= mem_req
->getPaddr();
294 checked_flags
= true;
298 * We don't actually check memory for the store because there
299 * is no guarantee it has left the lsq yet, and therefore we
300 * can't verify the memory on stores without lsq snooping
301 * enabled. This is left as future work for the Checker: LSQ snooping
302 * and memory validation after stores have committed.
304 bool was_prefetch
= mem_req
->isPrefetch();
306 //If we don't need to access a second cache line, stop now.
307 if (fault
!= NoFault
|| size_left
== 0)
309 if (fault
!= NoFault
&& was_prefetch
) {
315 frag_addr
+= frag_size
;
319 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
320 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
321 unverifiedReq
->getFlags(), frag_addr
, pAddr
, flags
);
325 // Assume the result was the same as the one passed in. This checker
326 // doesn't check if the SC should succeed or fail, it just checks the
328 if (unverifiedReq
&& res
&& unverifiedReq
->extraDataValid())
329 *res
= unverifiedReq
->getExtraData();
331 // Entire purpose here is to make sure we are getting the
332 // same data to send to the mem system as the CPU did.
333 // Cannot check this is actually what went to memory because
334 // there stores can be in ld/st queue or coherent operations
335 // overwriting values.
336 bool extraData
= false;
338 extraData
= unverifiedReq
->extraDataValid() ?
339 unverifiedReq
->getExtraData() : true;
342 // If the request is to ZERO a cache block, there is no data to check
343 // against, but it's all zero. We need something to compare to, so use a
344 // const set of zeros.
345 if (flags
& Request::STORE_NO_DATA
) {
347 assert(sizeof(zero_data
) <= size
);
351 if (unverifiedReq
&& unverifiedMemData
&&
352 memcmp(data
, unverifiedMemData
, size
) && extraData
) {
353 warn("%lli: Store value does not match value sent to memory! "
354 "data: %#x inst_data: %#x", curTick(), data
,
363 CheckerCPU::dbg_vtophys(Addr addr
)
365 return vtophys(tc
, addr
);
369 * Checks if the flags set by the Checker and Checkee match.
372 CheckerCPU::checkFlags(const RequestPtr
&unverified_req
, Addr vAddr
,
373 Addr pAddr
, int flags
)
375 Addr unverifiedVAddr
= unverified_req
->getVaddr();
376 Addr unverifiedPAddr
= unverified_req
->getPaddr();
377 int unverifiedFlags
= unverified_req
->getFlags();
379 if (unverifiedVAddr
!= vAddr
||
380 unverifiedPAddr
!= pAddr
||
381 unverifiedFlags
!= flags
) {
389 CheckerCPU::dumpAndExit()
391 warn("%lli: Checker PC:%s",
392 curTick(), thread
->pcState());
393 panic("Checker found an error!");