2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
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26 * this software without specific prior written permission.
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47 #include "arch/kernel_stats.hh"
48 #include "arch/vtophys.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "cpu/base.hh"
51 #include "cpu/simple_thread.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 #include "params/CheckerCPU.hh"
55 #include "sim/full_system.hh"
59 using namespace TheISA
;
64 masterId
= systemPtr
->getMasterId(name());
67 CheckerCPU::CheckerCPU(Params
*p
)
68 : BaseCPU(p
, true), systemPtr(NULL
), icachePort(NULL
), dcachePort(NULL
),
69 tc(NULL
), thread(NULL
)
73 curMacroStaticInst
= NULL
;
81 changedPC
= willChangePC
= changedNextPC
= false;
83 exitOnError
= p
->exitOnError
;
84 warnOnlyOnLoadError
= p
->warnOnlyOnLoadError
;
87 workload
= p
->workload
;
92 CheckerCPU::~CheckerCPU()
97 CheckerCPU::setSystem(System
*system
)
102 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
, false);
104 thread
= new SimpleThread(this, 0, systemPtr
,
105 workload
.size() ? workload
[0] : NULL
,
109 tc
= thread
->getTC();
110 threadContexts
.push_back(tc
);
111 thread
->kernelStats
= NULL
;
112 // Thread should never be null after this
113 assert(thread
!= NULL
);
117 CheckerCPU::setIcachePort(CpuPort
*icache_port
)
119 icachePort
= icache_port
;
123 CheckerCPU::setDcachePort(CpuPort
*dcache_port
)
125 dcachePort
= dcache_port
;
129 CheckerCPU::serialize(ostream
&os
)
134 CheckerCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
139 CheckerCPU::readMem(Addr addr
, uint8_t *data
, unsigned size
, unsigned flags
)
141 Fault fault
= NoFault
;
142 unsigned blockSize
= dcachePort
->peerBlockSize();
144 Addr secondAddr
= roundDown(addr
+ size
- 1, blockSize
);
145 bool checked_flags
= false;
146 bool flags_match
= true;
150 if (secondAddr
> addr
)
151 size
= secondAddr
- addr
;
153 // Need to account for multiple accesses like the Atomic and TimingSimple
155 memReq
= new Request();
156 memReq
->setVirt(0, addr
, size
, flags
, masterId
, thread
->pcState().instAddr());
158 // translate to physical address
159 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Read
);
161 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
162 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
163 memReq
->getPaddr(), memReq
->getFlags());
164 pAddr
= memReq
->getPaddr();
165 checked_flags
= true;
169 if (fault
== NoFault
&&
170 !memReq
->getFlags().isSet(Request::NO_ACCESS
)) {
171 PacketPtr pkt
= new Packet(memReq
,
173 MemCmd::LoadLockedReq
:
176 pkt
->dataStatic(data
);
178 if (!(memReq
->isUncacheable() || memReq
->isMmappedIpr())) {
179 // Access memory to see if we have the same data
180 dcachePort
->sendFunctional(pkt
);
182 // Assume the data is correct if it's an uncached access
183 memcpy(data
, unverifiedMemData
, size
);
191 if (fault
!= NoFault
) {
192 if (memReq
->isPrefetch()) {
200 if (memReq
!= NULL
) {
204 //If we don't need to access a second cache line, stop now.
205 if (secondAddr
<= addr
)
210 // Setup for accessing next cache line
212 unverifiedMemData
+= size
;
213 size
= addr
+ fullSize
- secondAddr
;
218 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
219 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
220 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
228 CheckerCPU::writeMem(uint8_t *data
, unsigned size
,
229 Addr addr
, unsigned flags
, uint64_t *res
)
231 Fault fault
= NoFault
;
232 bool checked_flags
= false;
233 bool flags_match
= true;
236 unsigned blockSize
= dcachePort
->peerBlockSize();
239 Addr secondAddr
= roundDown(addr
+ size
- 1, blockSize
);
241 if (secondAddr
> addr
)
242 size
= secondAddr
- addr
;
244 // Need to account for a multiple access like Atomic and Timing CPUs
246 memReq
= new Request();
247 memReq
->setVirt(0, addr
, size
, flags
, masterId
, thread
->pcState().instAddr());
249 // translate to physical address
250 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Write
);
252 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
253 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
254 memReq
->getPaddr(), memReq
->getFlags());
255 pAddr
= memReq
->getPaddr();
256 checked_flags
= true;
260 * We don't actually check memory for the store because there
261 * is no guarantee it has left the lsq yet, and therefore we
262 * can't verify the memory on stores without lsq snooping
263 * enabled. This is left as future work for the Checker: LSQ snooping
264 * and memory validation after stores have committed.
266 bool was_prefetch
= memReq
->isPrefetch();
270 //If we don't need to access a second cache line, stop now.
271 if (fault
!= NoFault
|| secondAddr
<= addr
)
273 if (fault
!= NoFault
&& was_prefetch
) {
279 //Update size and access address
280 size
= addr
+ fullSize
- secondAddr
;
281 //And access the right address.
286 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
287 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
288 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
292 // Assume the result was the same as the one passed in. This checker
293 // doesn't check if the SC should succeed or fail, it just checks the
295 if (unverifiedReq
&& res
&& unverifiedReq
->extraDataValid())
296 *res
= unverifiedReq
->getExtraData();
298 // Entire purpose here is to make sure we are getting the
299 // same data to send to the mem system as the CPU did.
300 // Cannot check this is actually what went to memory because
301 // there stores can be in ld/st queue or coherent operations
302 // overwriting values.
305 extraData
= unverifiedReq
->extraDataValid() ?
306 unverifiedReq
->getExtraData() : 1;
309 if (unverifiedReq
&& unverifiedMemData
&&
310 memcmp(data
, unverifiedMemData
, fullSize
) && extraData
) {
311 warn("%lli: Store value does not match value sent to memory!\
312 data: %#x inst_data: %#x", curTick(), data
,
321 CheckerCPU::dbg_vtophys(Addr addr
)
323 return vtophys(tc
, addr
);
327 * Checks if the flags set by the Checker and Checkee match.
330 CheckerCPU::checkFlags(Request
*unverified_req
, Addr vAddr
,
331 Addr pAddr
, int flags
)
333 Addr unverifiedVAddr
= unverified_req
->getVaddr();
334 Addr unverifiedPAddr
= unverified_req
->getPaddr();
335 int unverifiedFlags
= unverified_req
->getFlags();
337 if (unverifiedVAddr
!= vAddr
||
338 unverifiedPAddr
!= pAddr
||
339 unverifiedFlags
!= flags
) {
347 CheckerCPU::dumpAndExit()
349 warn("%lli: Checker PC:%s",
350 curTick(), thread
->pcState());
351 panic("Checker found an error!");