src/cpu/checker/cpu.cc

   1 /*
   2  * Copyright (c) 2011,2013,2017-2018 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #include "cpu/checker/cpu.hh"
  42
  43 #include <list>
  44 #include <string>
  45
  46 #include "arch/generic/tlb.hh"
  47 #include "arch/vtophys.hh"
  48 #include "cpu/base.hh"
  49 #include "cpu/simple_thread.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "cpu/thread_context.hh"
  52 #include "cpu/utils.hh"
  53 #include "params/CheckerCPU.hh"
  54 #include "sim/full_system.hh"
  55
  56 using namespace std;
  57 using namespace TheISA;
  58
  59 void
  60 CheckerCPU::init()
  61 {
  62     masterId = systemPtr->getMasterId(this);
  63 }
  64
  65 CheckerCPU::CheckerCPU(Params *p)
  66     : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
  67       tc(NULL), thread(NULL),
  68       unverifiedReq(nullptr),
  69       unverifiedMemData(nullptr)
  70 {
  71     curStaticInst = NULL;
  72     curMacroStaticInst = NULL;
  73
  74     numInst = 0;
  75     startNumInst = 0;
  76     numLoad = 0;
  77     startNumLoad = 0;
  78     youngestSN = 0;
  79
  80     changedPC = willChangePC = false;
  81
  82     exitOnError = p->exitOnError;
  83     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
  84     itb = p->itb;
  85     dtb = p->dtb;
  86     workload = p->workload;
  87
  88     updateOnError = true;
  89 }
  90
  91 CheckerCPU::~CheckerCPU()
  92 {
  93 }
  94
  95 void
  96 CheckerCPU::setSystem(System *system)
  97 {
  98     const Params *p(dynamic_cast<const Params *>(_params));
  99
 100     systemPtr = system;
 101
 102     if (FullSystem) {
 103         thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
 104                                   p->isa[0], false);
 105     } else {
 106         thread = new SimpleThread(this, 0, systemPtr,
 107                                   workload.size() ? workload[0] : NULL,
 108                                   itb, dtb, p->isa[0]);
 109     }
 110
 111     tc = thread->getTC();
 112     threadContexts.push_back(tc);
 113     thread->kernelStats = NULL;
 114     // Thread should never be null after this
 115     assert(thread != NULL);
 116 }
 117
 118 void
 119 CheckerCPU::setIcachePort(MasterPort *icache_port)
 120 {
 121     icachePort = icache_port;
 122 }
 123
 124 void
 125 CheckerCPU::setDcachePort(MasterPort *dcache_port)
 126 {
 127     dcachePort = dcache_port;
 128 }
 129
 130 void
 131 CheckerCPU::serialize(ostream &os) const
 132 {
 133 }
 134
 135 void
 136 CheckerCPU::unserialize(CheckpointIn &cp)
 137 {
 138 }
 139
 140 RequestPtr
 141 CheckerCPU::genMemFragmentRequest(Addr frag_addr, int size,
 142                                   Request::Flags flags,
 143                                   const std::vector<bool>& byte_enable,
 144                                   int& frag_size, int& size_left) const
 145 {
 146     frag_size = std::min(
 147         cacheLineSize() - addrBlockOffset(frag_addr, cacheLineSize()),
 148         (Addr) size_left);
 149     size_left -= frag_size;
 150
 151     RequestPtr mem_req;
 152
 153     if (!byte_enable.empty()) {
 154         // Set up byte-enable mask for the current fragment
 155         auto it_start = byte_enable.cbegin() + (size - (frag_size +
 156                                                         size_left));
 157         auto it_end = byte_enable.cbegin() + (size - size_left);
 158         if (isAnyActiveElement(it_start, it_end)) {
 159             mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
 160                     flags, masterId, thread->pcState().instAddr(),
 161                     tc->contextId());
 162             mem_req->setByteEnable(std::vector<bool>(it_start, it_end));
 163         }
 164     } else {
 165         mem_req = std::make_shared<Request>(0, frag_addr, frag_size,
 166                     flags, masterId, thread->pcState().instAddr(),
 167                     tc->contextId());
 168     }
 169
 170     return mem_req;
 171 }
 172
 173 Fault
 174 CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size,
 175                     Request::Flags flags,
 176                     const std::vector<bool>& byte_enable)
 177 {
 178     assert(byte_enable.empty() || byte_enable.size() == size);
 179
 180     Fault fault = NoFault;
 181     bool checked_flags = false;
 182     bool flags_match = true;
 183     Addr pAddr = 0x0;
 184
 185     Addr frag_addr = addr;
 186     int frag_size = 0;
 187     int size_left = size;
 188     bool predicate;
 189
 190     // Need to account for multiple accesses like the Atomic and TimingSimple
 191     while (1) {
 192         RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
 193                                                    byte_enable, frag_size,
 194                                                    size_left);
 195
 196         predicate = (mem_req != nullptr);
 197
 198         // translate to physical address
 199         if (predicate) {
 200             fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
 201         }
 202
 203         if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
 204             flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
 205                                      mem_req->getPaddr(), mem_req->getFlags());
 206             pAddr = mem_req->getPaddr();
 207             checked_flags = true;
 208         }
 209
 210         // Now do the access
 211         if (predicate && fault == NoFault &&
 212             !mem_req->getFlags().isSet(Request::NO_ACCESS)) {
 213             PacketPtr pkt = Packet::createRead(mem_req);
 214
 215             pkt->dataStatic(data);
 216
 217             if (!(mem_req->isUncacheable() || mem_req->isMmappedIpr())) {
 218                 // Access memory to see if we have the same data
 219                 dcachePort->sendFunctional(pkt);
 220             } else {
 221                 // Assume the data is correct if it's an uncached access
 222                 memcpy(data, unverifiedMemData, frag_size);
 223             }
 224
 225             delete pkt;
 226         }
 227
 228         if (fault != NoFault) {
 229             if (mem_req->isPrefetch()) {
 230                 fault = NoFault;
 231             }
 232             break;
 233         }
 234
 235         //If we don't need to access a second cache line, stop now.
 236         if (size_left == 0)
 237         {
 238             break;
 239         }
 240
 241         // Setup for accessing next cache line
 242         frag_addr += frag_size;
 243         data += frag_size;
 244         unverifiedMemData += frag_size;
 245     }
 246
 247     if (!flags_match) {
 248         warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
 249              curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 250              unverifiedReq->getFlags(), frag_addr, pAddr, flags);
 251         handleError();
 252     }
 253
 254     return fault;
 255 }
 256
 257 Fault
 258 CheckerCPU::writeMem(uint8_t *data, unsigned size,
 259                      Addr addr, Request::Flags flags, uint64_t *res,
 260                      const std::vector<bool>& byte_enable)
 261 {
 262     assert(byte_enable.empty() || byte_enable.size() == size);
 263
 264     Fault fault = NoFault;
 265     bool checked_flags = false;
 266     bool flags_match = true;
 267     Addr pAddr = 0x0;
 268     static uint8_t zero_data[64] = {};
 269
 270     Addr frag_addr = addr;
 271     int frag_size = 0;
 272     int size_left = size;
 273     bool predicate;
 274
 275     // Need to account for a multiple access like Atomic and Timing CPUs
 276     while (1) {
 277         RequestPtr mem_req = genMemFragmentRequest(frag_addr, size, flags,
 278                                                    byte_enable, frag_size,
 279                                                    size_left);
 280
 281         predicate = (mem_req != nullptr);
 282
 283         if (predicate) {
 284             fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
 285         }
 286
 287         if (predicate && !checked_flags && fault == NoFault && unverifiedReq) {
 288            flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
 289                                     mem_req->getPaddr(), mem_req->getFlags());
 290            pAddr = mem_req->getPaddr();
 291            checked_flags = true;
 292         }
 293
 294         /*
 295          * We don't actually check memory for the store because there
 296          * is no guarantee it has left the lsq yet, and therefore we
 297          * can't verify the memory on stores without lsq snooping
 298          * enabled.  This is left as future work for the Checker: LSQ snooping
 299          * and memory validation after stores have committed.
 300          */
 301         bool was_prefetch = mem_req->isPrefetch();
 302
 303         //If we don't need to access a second cache line, stop now.
 304         if (fault != NoFault || size_left == 0)
 305         {
 306             if (fault != NoFault && was_prefetch) {
 307               fault = NoFault;
 308             }
 309             break;
 310         }
 311
 312         frag_addr += frag_size;
 313    }
 314
 315    if (!flags_match) {
 316        warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
 317             curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 318             unverifiedReq->getFlags(), frag_addr, pAddr, flags);
 319        handleError();
 320    }
 321
 322    // Assume the result was the same as the one passed in.  This checker
 323    // doesn't check if the SC should succeed or fail, it just checks the
 324    // value.
 325    if (unverifiedReq && res && unverifiedReq->extraDataValid())
 326        *res = unverifiedReq->getExtraData();
 327
 328    // Entire purpose here is to make sure we are getting the
 329    // same data to send to the mem system as the CPU did.
 330    // Cannot check this is actually what went to memory because
 331    // there stores can be in ld/st queue or coherent operations
 332    // overwriting values.
 333    bool extraData = false;
 334    if (unverifiedReq) {
 335        extraData = unverifiedReq->extraDataValid() ?
 336                         unverifiedReq->getExtraData() : true;
 337    }
 338
 339    // If the request is to ZERO a cache block, there is no data to check
 340    // against, but it's all zero. We need something to compare to, so use a
 341    // const set of zeros.
 342    if (flags & Request::STORE_NO_DATA) {
 343        assert(!data);
 344        assert(sizeof(zero_data) <= size);
 345        data = zero_data;
 346    }
 347
 348    if (unverifiedReq && unverifiedMemData &&
 349        memcmp(data, unverifiedMemData, size) && extraData) {
 350            warn("%lli: Store value does not match value sent to memory! "
 351                   "data: %#x inst_data: %#x", curTick(), data,
 352                   unverifiedMemData);
 353        handleError();
 354    }
 355
 356    return fault;
 357 }
 358
 359 Addr
 360 CheckerCPU::dbg_vtophys(Addr addr)
 361 {
 362     return vtophys(tc, addr);
 363 }
 364
 365 /**
 366  * Checks if the flags set by the Checker and Checkee match.
 367  */
 368 bool
 369 CheckerCPU::checkFlags(const RequestPtr &unverified_req, Addr vAddr,
 370                        Addr pAddr, int flags)
 371 {
 372     Addr unverifiedVAddr = unverified_req->getVaddr();
 373     Addr unverifiedPAddr = unverified_req->getPaddr();
 374     int unverifiedFlags = unverified_req->getFlags();
 375
 376     if (unverifiedVAddr != vAddr ||
 377         unverifiedPAddr != pAddr ||
 378         unverifiedFlags != flags) {
 379         return false;
 380     }
 381
 382     return true;
 383 }
 384
 385 void
 386 CheckerCPU::dumpAndExit()
 387 {
 388     warn("%lli: Checker PC:%s",
 389          curTick(), thread->pcState());
 390     panic("Checker found an error!");
 391 }