src/cpu/checker/cpu.cc

   1 /*
   2  * Copyright (c) 2011,2013 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Kevin Lim
  41  *          Geoffrey Blake
  42  */
  43
  44 #include <list>
  45 #include <string>
  46
  47 #include "arch/kernel_stats.hh"
  48 #include "arch/vtophys.hh"
  49 #include "cpu/checker/cpu.hh"
  50 #include "cpu/base.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/static_inst.hh"
  53 #include "cpu/thread_context.hh"
  54 #include "params/CheckerCPU.hh"
  55 #include "sim/full_system.hh"
  56 #include "sim/tlb.hh"
  57
  58 using namespace std;
  59 using namespace TheISA;
  60
  61 void
  62 CheckerCPU::init()
  63 {
  64     masterId = systemPtr->getMasterId(name());
  65 }
  66
  67 CheckerCPU::CheckerCPU(Params *p)
  68     : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
  69       tc(NULL), thread(NULL)
  70 {
  71     memReq = NULL;
  72     curStaticInst = NULL;
  73     curMacroStaticInst = NULL;
  74
  75     numInst = 0;
  76     startNumInst = 0;
  77     numLoad = 0;
  78     startNumLoad = 0;
  79     youngestSN = 0;
  80
  81     changedPC = willChangePC = changedNextPC = false;
  82
  83     exitOnError = p->exitOnError;
  84     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
  85     itb = p->itb;
  86     dtb = p->dtb;
  87     workload = p->workload;
  88
  89     updateOnError = true;
  90 }
  91
  92 CheckerCPU::~CheckerCPU()
  93 {
  94 }
  95
  96 void
  97 CheckerCPU::setSystem(System *system)
  98 {
  99     const Params *p(dynamic_cast<const Params *>(_params));
 100
 101     systemPtr = system;
 102
 103     if (FullSystem) {
 104         thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
 105                                   p->isa[0], false);
 106     } else {
 107         thread = new SimpleThread(this, 0, systemPtr,
 108                                   workload.size() ? workload[0] : NULL,
 109                                   itb, dtb, p->isa[0]);
 110     }
 111
 112     tc = thread->getTC();
 113     threadContexts.push_back(tc);
 114     thread->kernelStats = NULL;
 115     // Thread should never be null after this
 116     assert(thread != NULL);
 117 }
 118
 119 void
 120 CheckerCPU::setIcachePort(MasterPort *icache_port)
 121 {
 122     icachePort = icache_port;
 123 }
 124
 125 void
 126 CheckerCPU::setDcachePort(MasterPort *dcache_port)
 127 {
 128     dcachePort = dcache_port;
 129 }
 130
 131 void
 132 CheckerCPU::serialize(ostream &os)
 133 {
 134 }
 135
 136 void
 137 CheckerCPU::unserialize(Checkpoint *cp, const string &section)
 138 {
 139 }
 140
 141 Fault
 142 CheckerCPU::readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags)
 143 {
 144     Fault fault = NoFault;
 145     int fullSize = size;
 146     Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
 147     bool checked_flags = false;
 148     bool flags_match = true;
 149     Addr pAddr = 0x0;
 150
 151
 152     if (secondAddr > addr)
 153        size = secondAddr - addr;
 154
 155     // Need to account for multiple accesses like the Atomic and TimingSimple
 156     while (1) {
 157         memReq = new Request();
 158         memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
 159
 160         // translate to physical address
 161         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
 162
 163         if (!checked_flags && fault == NoFault && unverifiedReq) {
 164             flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
 165                                      memReq->getPaddr(), memReq->getFlags());
 166             pAddr = memReq->getPaddr();
 167             checked_flags = true;
 168         }
 169
 170         // Now do the access
 171         if (fault == NoFault &&
 172             !memReq->getFlags().isSet(Request::NO_ACCESS)) {
 173             PacketPtr pkt = new Packet(memReq,
 174                                        memReq->isLLSC() ?
 175                                        MemCmd::LoadLockedReq :
 176                                        MemCmd::ReadReq);
 177
 178             pkt->dataStatic(data);
 179
 180             if (!(memReq->isUncacheable() || memReq->isMmappedIpr())) {
 181                 // Access memory to see if we have the same data
 182                 dcachePort->sendFunctional(pkt);
 183             } else {
 184                 // Assume the data is correct if it's an uncached access
 185                 memcpy(data, unverifiedMemData, size);
 186             }
 187
 188             delete memReq;
 189             memReq = NULL;
 190             delete pkt;
 191         }
 192
 193         if (fault != NoFault) {
 194             if (memReq->isPrefetch()) {
 195                 fault = NoFault;
 196             }
 197             delete memReq;
 198             memReq = NULL;
 199             break;
 200         }
 201
 202         if (memReq != NULL) {
 203             delete memReq;
 204         }
 205
 206         //If we don't need to access a second cache line, stop now.
 207         if (secondAddr <= addr)
 208         {
 209             break;
 210         }
 211
 212         // Setup for accessing next cache line
 213         data += size;
 214         unverifiedMemData += size;
 215         size = addr + fullSize - secondAddr;
 216         addr = secondAddr;
 217     }
 218
 219     if (!flags_match) {
 220         warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
 221              curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 222              unverifiedReq->getFlags(), addr, pAddr, flags);
 223         handleError();
 224     }
 225
 226     return fault;
 227 }
 228
 229 Fault
 230 CheckerCPU::writeMem(uint8_t *data, unsigned size,
 231                      Addr addr, unsigned flags, uint64_t *res)
 232 {
 233     Fault fault = NoFault;
 234     bool checked_flags = false;
 235     bool flags_match = true;
 236     Addr pAddr = 0x0;
 237
 238     int fullSize = size;
 239
 240     Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
 241
 242     if (secondAddr > addr)
 243         size = secondAddr - addr;
 244
 245     // Need to account for a multiple access like Atomic and Timing CPUs
 246     while (1) {
 247         memReq = new Request();
 248         memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
 249
 250         // translate to physical address
 251         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
 252
 253         if (!checked_flags && fault == NoFault && unverifiedReq) {
 254            flags_match = checkFlags(unverifiedReq, memReq->getVaddr(),
 255                                     memReq->getPaddr(), memReq->getFlags());
 256            pAddr = memReq->getPaddr();
 257            checked_flags = true;
 258         }
 259
 260         /*
 261          * We don't actually check memory for the store because there
 262          * is no guarantee it has left the lsq yet, and therefore we
 263          * can't verify the memory on stores without lsq snooping
 264          * enabled.  This is left as future work for the Checker: LSQ snooping
 265          * and memory validation after stores have committed.
 266          */
 267         bool was_prefetch = memReq->isPrefetch();
 268
 269         delete memReq;
 270
 271         //If we don't need to access a second cache line, stop now.
 272         if (fault != NoFault || secondAddr <= addr)
 273         {
 274             if (fault != NoFault && was_prefetch) {
 275               fault = NoFault;
 276             }
 277             break;
 278         }
 279
 280         //Update size and access address
 281         size = addr + fullSize - secondAddr;
 282         //And access the right address.
 283         addr = secondAddr;
 284    }
 285
 286    if (!flags_match) {
 287        warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
 288             curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
 289             unverifiedReq->getFlags(), addr, pAddr, flags);
 290        handleError();
 291    }
 292
 293    // Assume the result was the same as the one passed in.  This checker
 294    // doesn't check if the SC should succeed or fail, it just checks the
 295    // value.
 296    if (unverifiedReq && res && unverifiedReq->extraDataValid())
 297        *res = unverifiedReq->getExtraData();
 298
 299    // Entire purpose here is to make sure we are getting the
 300    // same data to send to the mem system as the CPU did.
 301    // Cannot check this is actually what went to memory because
 302    // there stores can be in ld/st queue or coherent operations
 303    // overwriting values.
 304    bool extraData;
 305    if (unverifiedReq) {
 306        extraData = unverifiedReq->extraDataValid() ?
 307                         unverifiedReq->getExtraData() : 1;
 308    }
 309
 310    if (unverifiedReq && unverifiedMemData &&
 311        memcmp(data, unverifiedMemData, fullSize) && extraData) {
 312            warn("%lli: Store value does not match value sent to memory!\
 313                   data: %#x inst_data: %#x", curTick(), data,
 314                   unverifiedMemData);
 315        handleError();
 316    }
 317
 318    return fault;
 319 }
 320
 321 Addr
 322 CheckerCPU::dbg_vtophys(Addr addr)
 323 {
 324     return vtophys(tc, addr);
 325 }
 326
 327 /**
 328  * Checks if the flags set by the Checker and Checkee match.
 329  */
 330 bool
 331 CheckerCPU::checkFlags(Request *unverified_req, Addr vAddr,
 332                        Addr pAddr, int flags)
 333 {
 334     Addr unverifiedVAddr = unverified_req->getVaddr();
 335     Addr unverifiedPAddr = unverified_req->getPaddr();
 336     int unverifiedFlags = unverified_req->getFlags();
 337
 338     if (unverifiedVAddr != vAddr ||
 339         unverifiedPAddr != pAddr ||
 340         unverifiedFlags != flags) {
 341         return false;
 342     }
 343
 344     return true;
 345 }
 346
 347 void
 348 CheckerCPU::dumpAndExit()
 349 {
 350     warn("%lli: Checker PC:%s",
 351          curTick(), thread->pcState());
 352     panic("Checker found an error!");
 353 }