b1167c1d8fc9fb984b4b33cee1e2c42fcf782ce6
2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
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9 * redistributions in binary form must reproduce the above copyright
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12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include "base/refcnt.hh"
35 #include "cpu/base.hh"
36 #include "cpu/base_dyn_inst.hh"
37 #include "cpu/checker/cpu.hh"
38 #include "cpu/simple_thread.hh"
39 #include "cpu/thread_context.hh"
40 #include "cpu/static_inst.hh"
41 #include "sim/byteswap.hh"
42 #include "sim/sim_object.hh"
43 #include "sim/stats.hh"
45 #include "cpu/o3/alpha_dyn_inst.hh"
46 #include "cpu/o3/alpha_impl.hh"
48 //#include "cpu/ozone/dyn_inst.hh"
49 //#include "cpu/ozone/ozone_impl.hh"
50 //#include "cpu/ozone/simple_impl.hh"
53 #include "sim/system.hh"
54 #include "arch/vtophys.hh"
58 //The CheckerCPU does alpha only
59 using namespace AlphaISA
;
66 CheckerCPU::CheckerCPU(Params
*p
)
67 : BaseCPU(p
), thread(NULL
), tc(NULL
)
77 changedPC
= willChangePC
= changedNextPC
= false;
79 exitOnError
= p
->exitOnError
;
91 CheckerCPU::~CheckerCPU()
96 CheckerCPU::setMemory(MemObject
*mem
)
100 thread
= new SimpleThread(this, /* thread_num */ 0, process
,
103 thread
->setStatus(ThreadContext::Suspended
);
104 tc
= thread
->getTC();
105 threadContexts
.push_back(tc
);
110 CheckerCPU::setSystem(System
*system
)
115 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
, false);
117 thread
->setStatus(ThreadContext::Suspended
);
118 tc
= thread
->getTC();
119 threadContexts
.push_back(tc
);
120 delete thread
->kernelStats
;
121 thread
->kernelStats
= NULL
;
126 CheckerCPU::setIcachePort(Port
*icache_port
)
128 icachePort
= icache_port
;
132 CheckerCPU::setDcachePort(Port
*dcache_port
)
134 dcachePort
= dcache_port
;
138 CheckerCPU::serialize(ostream
&os
)
141 BaseCPU::serialize(os);
142 SERIALIZE_SCALAR(inst);
143 nameOut(os, csprintf("%s.xc", name()));
144 thread->serialize(os);
145 cacheCompletionEvent.serialize(os);
150 CheckerCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
153 BaseCPU::unserialize(cp, section);
154 UNSERIALIZE_SCALAR(inst);
155 thread->unserialize(cp, csprintf("%s.xc", section));
160 CheckerCPU::copySrcTranslate(Addr src
)
162 panic("Unimplemented!");
166 CheckerCPU::copy(Addr dest
)
168 panic("Unimplemented!");
173 CheckerCPU::read(Addr addr
, T
&data
, unsigned flags
)
175 // need to fill in CPU & thread IDs here
176 memReq
= new Request();
178 memReq
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
180 // translate to physical address
181 translateDataReadReq(memReq
);
183 Packet
*pkt
= new Packet(memReq
, Packet::ReadReq
, Packet::Broadcast
);
185 pkt
->dataStatic(&data
);
187 if (!(memReq
->getFlags() & UNCACHEABLE
)) {
188 // Access memory to see if we have the same data
189 dcachePort
->sendFunctional(pkt
);
191 // Assume the data is correct if it's an uncached access
192 memcpy(&data
, &unverifiedResult
.integer
, sizeof(T
));
200 #ifndef DOXYGEN_SHOULD_SKIP_THIS
204 CheckerCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
208 CheckerCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
212 CheckerCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
216 CheckerCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
218 #endif //DOXYGEN_SHOULD_SKIP_THIS
222 CheckerCPU::read(Addr addr
, double &data
, unsigned flags
)
224 return read(addr
, *(uint64_t*)&data
, flags
);
229 CheckerCPU::read(Addr addr
, float &data
, unsigned flags
)
231 return read(addr
, *(uint32_t*)&data
, flags
);
236 CheckerCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
238 return read(addr
, (uint32_t&)data
, flags
);
243 CheckerCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
245 // need to fill in CPU & thread IDs here
246 memReq
= new Request();
248 memReq
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
250 // translate to physical address
251 thread
->translateDataWriteReq(memReq
);
253 // Can compare the write data and result only if it's cacheable,
254 // not a store conditional, or is a store conditional that
256 // @todo: Verify that actual memory matches up with these values.
257 // Right now it only verifies that the instruction data is the
258 // same as what was in the request that got sent to memory; there
259 // is no verification that it is the same as what is in memory.
260 // This is because the LSQ would have to be snooped in the CPU to
263 !(unverifiedReq
->getFlags() & UNCACHEABLE
) &&
264 (!(unverifiedReq
->getFlags() & LOCKED
) ||
265 ((unverifiedReq
->getFlags() & LOCKED
) &&
266 unverifiedReq
->getScResult() == 1))) {
269 // This code would work if the LSQ allowed for snooping.
270 Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
271 pkt.dataStatic(&inst_data);
273 dcachePort->sendFunctional(pkt);
277 memcpy(&inst_data
, unverifiedMemData
, sizeof(T
));
279 if (data
!= inst_data
) {
280 warn("%lli: Store value does not match value in memory! "
281 "Instruction: %#x, memory: %#x",
282 curTick
, inst_data
, data
);
287 // Assume the result was the same as the one passed in. This checker
288 // doesn't check if the SC should succeed or fail, it just checks the
290 if (res
&& unverifiedReq
->scResultValid())
291 *res
= unverifiedReq
->getScResult();
297 #ifndef DOXYGEN_SHOULD_SKIP_THIS
300 CheckerCPU::write(uint64_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
304 CheckerCPU::write(uint32_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
308 CheckerCPU::write(uint16_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
312 CheckerCPU::write(uint8_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
314 #endif //DOXYGEN_SHOULD_SKIP_THIS
318 CheckerCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
320 return write(*(uint64_t*)&data
, addr
, flags
, res
);
325 CheckerCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
327 return write(*(uint32_t*)&data
, addr
, flags
, res
);
332 CheckerCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
334 return write((uint32_t)data
, addr
, flags
, res
);
340 CheckerCPU::dbg_vtophys(Addr addr
)
342 return vtophys(tc
, addr
);
344 #endif // FULL_SYSTEM
347 CheckerCPU::translateInstReq(Request
*req
)
350 return (thread
->translateInstReq(req
) == NoFault
);
352 thread
->translateInstReq(req
);
358 CheckerCPU::translateDataReadReq(Request
*req
)
360 thread
->translateDataReadReq(req
);
362 if (req
->getVaddr() != unverifiedReq
->getVaddr()) {
363 warn("%lli: Request virtual addresses do not match! Inst: %#x, "
365 curTick
, unverifiedReq
->getVaddr(), req
->getVaddr());
368 req
->setPaddr(unverifiedReq
->getPaddr());
370 if (checkFlags(req
)) {
371 warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
372 curTick
, unverifiedReq
->getFlags(), req
->getFlags());
378 CheckerCPU::translateDataWriteReq(Request
*req
)
380 thread
->translateDataWriteReq(req
);
382 if (req
->getVaddr() != unverifiedReq
->getVaddr()) {
383 warn("%lli: Request virtual addresses do not match! Inst: %#x, "
385 curTick
, unverifiedReq
->getVaddr(), req
->getVaddr());
388 req
->setPaddr(unverifiedReq
->getPaddr());
390 if (checkFlags(req
)) {
391 warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
392 curTick
, unverifiedReq
->getFlags(), req
->getFlags());
398 CheckerCPU::checkFlags(Request
*req
)
400 // Remove any dynamic flags that don't have to do with the request itself.
401 unsigned flags
= unverifiedReq
->getFlags();
402 unsigned mask
= LOCKED
| PHYSICAL
| VPTE
| ALTMODE
| UNCACHEABLE
| NO_FAULT
;
403 flags
= flags
& (mask
);
404 if (flags
== req
->getFlags()) {
411 template <class DynInstPtr
>
413 Checker
<DynInstPtr
>::tick(DynInstPtr
&completed_inst
)
417 // Either check this instruction, or add it to a list of
418 // instructions waiting to be checked. Instructions must be
419 // checked in program order, so if a store has committed yet not
420 // completed, there may be some instructions that are waiting
421 // behind it that have completed and must be checked.
422 if (!instList
.empty()) {
423 if (youngestSN
< completed_inst
->seqNum
) {
424 DPRINTF(Checker
, "Adding instruction [sn:%lli] PC:%#x to list.\n",
425 completed_inst
->seqNum
, completed_inst
->readPC());
426 instList
.push_back(completed_inst
);
427 youngestSN
= completed_inst
->seqNum
;
430 if (!instList
.front()->isCompleted()) {
433 inst
= instList
.front();
434 instList
.pop_front();
437 if (!completed_inst
->isCompleted()) {
438 if (youngestSN
< completed_inst
->seqNum
) {
439 DPRINTF(Checker
, "Adding instruction [sn:%lli] PC:%#x to list.\n",
440 completed_inst
->seqNum
, completed_inst
->readPC());
441 instList
.push_back(completed_inst
);
442 youngestSN
= completed_inst
->seqNum
;
446 if (youngestSN
< completed_inst
->seqNum
) {
447 inst
= completed_inst
;
448 youngestSN
= completed_inst
->seqNum
;
455 // Try to check all instructions that are completed, ending if we
456 // run out of instructions to check or if an instruction is not
459 DPRINTF(Checker
, "Processing instruction [sn:%lli] PC:%#x.\n",
460 inst
->seqNum
, inst
->readPC());
461 unverifiedResult
.integer
= inst
->readIntResult();
462 unverifiedReq
= inst
->req
;
463 unverifiedMemData
= inst
->memData
;
466 Fault fault
= NoFault
;
468 // maintain $r0 semantics
469 thread
->setIntReg(ZeroReg
, 0);
471 thread
->setFloatRegDouble(ZeroReg
, 0.0);
472 #endif // TARGET_ALPHA
474 // Check if any recent PC changes match up with anything we
475 // expect to happen. This is mostly to check if traps or
476 // PC-based events have occurred in both the checker and CPU.
478 DPRINTF(Checker
, "Changed PC recently to %#x\n",
481 if (newPC
== thread
->readPC()) {
482 DPRINTF(Checker
, "Changed PC matches expected PC\n");
484 warn("%lli: Changed PC does not match expected PC, "
485 "changed: %#x, expected: %#x",
486 curTick
, thread
->readPC(), newPC
);
489 willChangePC
= false;
494 DPRINTF(Checker
, "Changed NextPC recently to %#x\n",
495 thread
->readNextPC());
496 changedNextPC
= false;
499 // Try to fetch the instruction
502 #define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
504 #define IFETCH_FLAGS(pc) 0
507 uint64_t fetch_PC
= thread
->readPC() & ~3;
509 // set up memory request for instruction fetch
510 memReq
= new Request(inst
->threadNumber
, fetch_PC
,
512 IFETCH_FLAGS(thread
->readPC()),
513 fetch_PC
, thread
->readCpuId(), inst
->threadNumber
);
515 bool succeeded
= translateInstReq(memReq
);
518 if (inst
->getFault() == NoFault
) {
519 // In this case the instruction was not a dummy
520 // instruction carrying an ITB fault. In the single
521 // threaded case the ITB should still be able to
522 // translate this instruction; in the SMT case it's
523 // possible that its ITB entry was kicked out.
524 warn("%lli: Instruction PC %#x was not found in the ITB!",
525 curTick
, thread
->readPC());
528 // go to the next instruction
529 thread
->setPC(thread
->readNextPC());
530 thread
->setNextPC(thread
->readNextPC() + sizeof(MachInst
));
534 // The instruction is carrying an ITB fault. Handle
535 // the fault and see if our results match the CPU on
537 fault
= inst
->getFault();
541 if (fault
== NoFault
) {
542 Packet
*pkt
= new Packet(memReq
, Packet::ReadReq
,
545 pkt
->dataStatic(&machInst
);
547 icachePort
->sendFunctional(pkt
);
551 // keep an instruction count
554 // decode the instruction
555 machInst
= gtoh(machInst
);
556 // Checks that the instruction matches what we expected it to be.
557 // Checks both the machine instruction and the PC.
560 curStaticInst
= StaticInst::decode(makeExtMI(machInst
,
564 thread
->setInst(machInst
);
565 #endif // FULL_SYSTEM
567 fault
= inst
->getFault();
570 // Discard fetch's memReq.
574 // Either the instruction was a fault and we should process the fault,
575 // or we should just go ahead execute the instruction. This assumes
576 // that the instruction is properly marked as a fault.
577 if (fault
== NoFault
) {
579 thread
->funcExeInst
++;
581 fault
= curStaticInst
->execute(this, NULL
);
583 // Checks to make sure instrution results are correct.
584 validateExecution(inst
);
586 if (curStaticInst
->isLoad()) {
591 if (fault
!= NoFault
) {
595 newPC
= thread
->readPC();
596 DPRINTF(Checker
, "Fault, PC is now %#x\n", newPC
);
597 #else // !FULL_SYSTEM
598 fatal("fault (%d) detected @ PC 0x%08p", fault
, thread
->readPC());
599 #endif // FULL_SYSTEM
601 #if THE_ISA != MIPS_ISA
602 // go to the next instruction
603 thread
->setPC(thread
->readNextPC());
604 thread
->setNextPC(thread
->readNextPC() + sizeof(MachInst
));
606 // go to the next instruction
607 thread
->setPC(thread
->readNextPC());
608 thread
->setNextPC(thread
->readNextNPC());
609 thread
->setNextNPC(thread
->readNextNPC() + sizeof(MachInst
));
615 // @todo: Determine if these should happen only if the
616 // instruction hasn't faulted. In the SimpleCPU case this may
617 // not be true, but in the O3 or Ozone case this may be true.
621 oldpc
= thread
->readPC();
622 system
->pcEventQueue
.service(tc
);
624 } while (oldpc
!= thread
->readPC());
627 newPC
= thread
->readPC();
628 DPRINTF(Checker
, "PC Event, PC is now %#x\n", newPC
);
632 // @todo: Optionally can check all registers. (Or just those
633 // that have been modified).
641 // Continue verifying instructions if there's another completed
642 // instruction waiting to be verified.
643 if (instList
.empty()) {
645 } else if (instList
.front()->isCompleted()) {
646 inst
= instList
.front();
647 instList
.pop_front();
654 template <class DynInstPtr
>
656 Checker
<DynInstPtr
>::switchOut(Sampler
*s
)
661 template <class DynInstPtr
>
663 Checker
<DynInstPtr
>::takeOverFrom(BaseCPU
*oldCPU
)
667 template <class DynInstPtr
>
669 Checker
<DynInstPtr
>::validateInst(DynInstPtr
&inst
)
671 if (inst
->readPC() != thread
->readPC()) {
672 warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
673 curTick
, inst
->readPC(), thread
->readPC());
675 warn("%lli: Changed PCs recently, may not be an error",
682 MachInst mi
= static_cast<MachInst
>(inst
->staticInst
->machInst
);
684 if (mi
!= machInst
) {
685 warn("%lli: Binary instructions do not match! Inst: %#x, "
687 curTick
, mi
, machInst
);
692 template <class DynInstPtr
>
694 Checker
<DynInstPtr
>::validateExecution(DynInstPtr
&inst
)
696 if (inst
->numDestRegs()) {
697 // @todo: Support more destination registers.
698 if (inst
->isUnverifiable()) {
699 // Unverifiable instructions assume they were executed
700 // properly by the CPU. Grab the result from the
701 // instruction and write it to the register.
702 RegIndex idx
= inst
->destRegIdx(0);
703 if (idx
< TheISA::FP_Base_DepTag
) {
704 thread
->setIntReg(idx
, inst
->readIntResult());
705 } else if (idx
< TheISA::Fpcr_DepTag
) {
706 thread
->setFloatRegBits(idx
, inst
->readIntResult());
708 thread
->setMiscReg(idx
, inst
->readIntResult());
710 } else if (result
.integer
!= inst
->readIntResult()) {
711 warn("%lli: Instruction results do not match! (Values may not "
712 "actually be integers) Inst: %#x, checker: %#x",
713 curTick
, inst
->readIntResult(), result
.integer
);
718 if (inst
->readNextPC() != thread
->readNextPC()) {
719 warn("%lli: Instruction next PCs do not match! Inst: %#x, "
721 curTick
, inst
->readNextPC(), thread
->readNextPC());
725 // Checking side effect registers can be difficult if they are not
726 // checked simultaneously with the execution of the instruction.
727 // This is because other valid instructions may have modified
728 // these registers in the meantime, and their values are not
729 // stored within the DynInst.
730 while (!miscRegIdxs
.empty()) {
731 int misc_reg_idx
= miscRegIdxs
.front();
734 if (inst
->tcBase()->readMiscReg(misc_reg_idx
) !=
735 thread
->readMiscReg(misc_reg_idx
)) {
736 warn("%lli: Misc reg idx %i (side effect) does not match! "
737 "Inst: %#x, checker: %#x",
738 curTick
, misc_reg_idx
,
739 inst
->tcBase()->readMiscReg(misc_reg_idx
),
740 thread
->readMiscReg(misc_reg_idx
));
746 template <class DynInstPtr
>
748 Checker
<DynInstPtr
>::validateState()
752 template <class DynInstPtr
>
754 Checker
<DynInstPtr
>::dumpInsts()
758 InstListIt inst_list_it
= --(instList
.end());
760 cprintf("Inst list size: %i\n", instList
.size());
762 while (inst_list_it
!= instList
.end())
764 cprintf("Instruction:%i\n",
767 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
769 (*inst_list_it
)->readPC(),
770 (*inst_list_it
)->seqNum
,
771 (*inst_list_it
)->threadNumber
,
772 (*inst_list_it
)->isCompleted());
783 //class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
786 class Checker
<RefCountingPtr
<AlphaDynInst
<AlphaSimpleImpl
> > >;