2 * Copyright (c) 2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
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26 * this software without specific prior written permission.
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47 #include "arch/kernel_stats.hh"
48 #include "arch/vtophys.hh"
49 #include "cpu/checker/cpu.hh"
50 #include "cpu/base.hh"
51 #include "cpu/simple_thread.hh"
52 #include "cpu/static_inst.hh"
53 #include "cpu/thread_context.hh"
54 #include "params/CheckerCPU.hh"
55 #include "sim/full_system.hh"
59 using namespace TheISA
;
64 masterId
= systemPtr
->getMasterId(name());
67 CheckerCPU::CheckerCPU(Params
*p
)
68 : BaseCPU(p
, true), systemPtr(NULL
), icachePort(NULL
), dcachePort(NULL
),
69 tc(NULL
), thread(NULL
)
73 curMacroStaticInst
= NULL
;
81 changedPC
= willChangePC
= changedNextPC
= false;
83 exitOnError
= p
->exitOnError
;
84 warnOnlyOnLoadError
= p
->warnOnlyOnLoadError
;
87 workload
= p
->workload
;
92 CheckerCPU::~CheckerCPU()
97 CheckerCPU::setSystem(System
*system
)
99 const Params
*p(dynamic_cast<const Params
*>(_params
));
104 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
,
107 thread
= new SimpleThread(this, 0, systemPtr
,
108 workload
.size() ? workload
[0] : NULL
,
109 itb
, dtb
, p
->isa
[0]);
112 tc
= thread
->getTC();
113 threadContexts
.push_back(tc
);
114 thread
->kernelStats
= NULL
;
115 // Thread should never be null after this
116 assert(thread
!= NULL
);
120 CheckerCPU::setIcachePort(CpuPort
*icache_port
)
122 icachePort
= icache_port
;
126 CheckerCPU::setDcachePort(CpuPort
*dcache_port
)
128 dcachePort
= dcache_port
;
132 CheckerCPU::serialize(ostream
&os
)
137 CheckerCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
142 CheckerCPU::readMem(Addr addr
, uint8_t *data
, unsigned size
, unsigned flags
)
144 Fault fault
= NoFault
;
145 unsigned blockSize
= dcachePort
->peerBlockSize();
147 Addr secondAddr
= roundDown(addr
+ size
- 1, blockSize
);
148 bool checked_flags
= false;
149 bool flags_match
= true;
153 if (secondAddr
> addr
)
154 size
= secondAddr
- addr
;
156 // Need to account for multiple accesses like the Atomic and TimingSimple
158 memReq
= new Request();
159 memReq
->setVirt(0, addr
, size
, flags
, masterId
, thread
->pcState().instAddr());
161 // translate to physical address
162 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Read
);
164 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
165 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
166 memReq
->getPaddr(), memReq
->getFlags());
167 pAddr
= memReq
->getPaddr();
168 checked_flags
= true;
172 if (fault
== NoFault
&&
173 !memReq
->getFlags().isSet(Request::NO_ACCESS
)) {
174 PacketPtr pkt
= new Packet(memReq
,
176 MemCmd::LoadLockedReq
:
179 pkt
->dataStatic(data
);
181 if (!(memReq
->isUncacheable() || memReq
->isMmappedIpr())) {
182 // Access memory to see if we have the same data
183 dcachePort
->sendFunctional(pkt
);
185 // Assume the data is correct if it's an uncached access
186 memcpy(data
, unverifiedMemData
, size
);
194 if (fault
!= NoFault
) {
195 if (memReq
->isPrefetch()) {
203 if (memReq
!= NULL
) {
207 //If we don't need to access a second cache line, stop now.
208 if (secondAddr
<= addr
)
213 // Setup for accessing next cache line
215 unverifiedMemData
+= size
;
216 size
= addr
+ fullSize
- secondAddr
;
221 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
222 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
223 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
231 CheckerCPU::writeMem(uint8_t *data
, unsigned size
,
232 Addr addr
, unsigned flags
, uint64_t *res
)
234 Fault fault
= NoFault
;
235 bool checked_flags
= false;
236 bool flags_match
= true;
239 unsigned blockSize
= dcachePort
->peerBlockSize();
242 Addr secondAddr
= roundDown(addr
+ size
- 1, blockSize
);
244 if (secondAddr
> addr
)
245 size
= secondAddr
- addr
;
247 // Need to account for a multiple access like Atomic and Timing CPUs
249 memReq
= new Request();
250 memReq
->setVirt(0, addr
, size
, flags
, masterId
, thread
->pcState().instAddr());
252 // translate to physical address
253 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Write
);
255 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
256 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
257 memReq
->getPaddr(), memReq
->getFlags());
258 pAddr
= memReq
->getPaddr();
259 checked_flags
= true;
263 * We don't actually check memory for the store because there
264 * is no guarantee it has left the lsq yet, and therefore we
265 * can't verify the memory on stores without lsq snooping
266 * enabled. This is left as future work for the Checker: LSQ snooping
267 * and memory validation after stores have committed.
269 bool was_prefetch
= memReq
->isPrefetch();
273 //If we don't need to access a second cache line, stop now.
274 if (fault
!= NoFault
|| secondAddr
<= addr
)
276 if (fault
!= NoFault
&& was_prefetch
) {
282 //Update size and access address
283 size
= addr
+ fullSize
- secondAddr
;
284 //And access the right address.
289 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
290 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
291 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
295 // Assume the result was the same as the one passed in. This checker
296 // doesn't check if the SC should succeed or fail, it just checks the
298 if (unverifiedReq
&& res
&& unverifiedReq
->extraDataValid())
299 *res
= unverifiedReq
->getExtraData();
301 // Entire purpose here is to make sure we are getting the
302 // same data to send to the mem system as the CPU did.
303 // Cannot check this is actually what went to memory because
304 // there stores can be in ld/st queue or coherent operations
305 // overwriting values.
308 extraData
= unverifiedReq
->extraDataValid() ?
309 unverifiedReq
->getExtraData() : 1;
312 if (unverifiedReq
&& unverifiedMemData
&&
313 memcmp(data
, unverifiedMemData
, fullSize
) && extraData
) {
314 warn("%lli: Store value does not match value sent to memory!\
315 data: %#x inst_data: %#x", curTick(), data
,
324 CheckerCPU::dbg_vtophys(Addr addr
)
326 return vtophys(tc
, addr
);
330 * Checks if the flags set by the Checker and Checkee match.
333 CheckerCPU::checkFlags(Request
*unverified_req
, Addr vAddr
,
334 Addr pAddr
, int flags
)
336 Addr unverifiedVAddr
= unverified_req
->getVaddr();
337 Addr unverifiedPAddr
= unverified_req
->getPaddr();
338 int unverifiedFlags
= unverified_req
->getFlags();
340 if (unverifiedVAddr
!= vAddr
||
341 unverifiedPAddr
!= pAddr
||
342 unverifiedFlags
!= flags
) {
350 CheckerCPU::dumpAndExit()
352 warn("%lli: Checker PC:%s",
353 curTick(), thread
->pcState());
354 panic("Checker found an error!");