src/cpu/checker/cpu.cc

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <list>
  30 #include <string>
  31
  32 #include "base/refcnt.hh"
  33 #include "cpu/base.hh"
  34 #include "cpu/base_dyn_inst.hh"
  35 #include "cpu/checker/cpu.hh"
  36 #include "cpu/simple_thread.hh"
  37 #include "cpu/thread_context.hh"
  38 #include "cpu/static_inst.hh"
  39 #include "sim/byteswap.hh"
  40 #include "sim/sim_object.hh"
  41 #include "sim/stats.hh"
  42
  43 #include "cpu/o3/alpha_dyn_inst.hh"
  44 #include "cpu/o3/alpha_impl.hh"
  45
  46 //#include "cpu/ozone/dyn_inst.hh"
  47 //#include "cpu/ozone/ozone_impl.hh"
  48 //#include "cpu/ozone/simple_impl.hh"
  49
  50 #if FULL_SYSTEM
  51 #include "sim/system.hh"
  52 #include "arch/vtophys.hh"
  53 #endif // FULL_SYSTEM
  54
  55 using namespace std;
  56 //The CheckerCPU does alpha only
  57 using namespace AlphaISA;
  58
  59 void
  60 CheckerCPU::init()
  61 {
  62 }
  63
  64 CheckerCPU::CheckerCPU(Params *p)
  65     : BaseCPU(p), thread(NULL), tc(NULL)
  66 {
  67     memReq = NULL;
  68
  69     numInst = 0;
  70     startNumInst = 0;
  71     numLoad = 0;
  72     startNumLoad = 0;
  73     youngestSN = 0;
  74
  75     changedPC = willChangePC = changedNextPC = false;
  76
  77     exitOnError = p->exitOnError;
  78 #if FULL_SYSTEM
  79     itb = p->itb;
  80     dtb = p->dtb;
  81     systemPtr = NULL;
  82     memPtr = NULL;
  83 #else
  84     process = p->process;
  85 #endif
  86 }
  87
  88 CheckerCPU::~CheckerCPU()
  89 {
  90 }
  91
  92 void
  93 CheckerCPU::setMemory(MemObject *mem)
  94 {
  95     memPtr = mem;
  96 #if !FULL_SYSTEM
  97     thread = new SimpleThread(this, /* thread_num */ 0, process,
  98                               /* asid */ 0, mem);
  99
 100     thread->setStatus(ThreadContext::Suspended);
 101     tc = thread->getTC();
 102     threadContexts.push_back(tc);
 103 #else
 104     if (systemPtr) {
 105         thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
 106
 107         thread->setStatus(ThreadContext::Suspended);
 108         tc = thread->getTC();
 109         threadContexts.push_back(tc);
 110         delete thread->kernelStats;
 111         thread->kernelStats = NULL;
 112     }
 113 #endif
 114 }
 115
 116 #if FULL_SYSTEM
 117 void
 118 CheckerCPU::setSystem(System *system)
 119 {
 120     systemPtr = system;
 121
 122     if (memPtr) {
 123         thread = new SimpleThread(this, 0, systemPtr, itb, dtb, memPtr, false);
 124
 125         thread->setStatus(ThreadContext::Suspended);
 126         tc = thread->getTC();
 127         threadContexts.push_back(tc);
 128         delete thread->kernelStats;
 129         thread->kernelStats = NULL;
 130     }
 131 }
 132 #endif
 133
 134 void
 135 CheckerCPU::setIcachePort(Port *icache_port)
 136 {
 137     icachePort = icache_port;
 138 }
 139
 140 void
 141 CheckerCPU::setDcachePort(Port *dcache_port)
 142 {
 143     dcachePort = dcache_port;
 144 }
 145
 146 void
 147 CheckerCPU::serialize(ostream &os)
 148 {
 149 /*
 150     BaseCPU::serialize(os);
 151     SERIALIZE_SCALAR(inst);
 152     nameOut(os, csprintf("%s.xc", name()));
 153     thread->serialize(os);
 154     cacheCompletionEvent.serialize(os);
 155 */
 156 }
 157
 158 void
 159 CheckerCPU::unserialize(Checkpoint *cp, const string &section)
 160 {
 161 /*
 162     BaseCPU::unserialize(cp, section);
 163     UNSERIALIZE_SCALAR(inst);
 164     thread->unserialize(cp, csprintf("%s.xc", section));
 165 */
 166 }
 167
 168 Fault
 169 CheckerCPU::copySrcTranslate(Addr src)
 170 {
 171     panic("Unimplemented!");
 172 }
 173
 174 Fault
 175 CheckerCPU::copy(Addr dest)
 176 {
 177     panic("Unimplemented!");
 178 }
 179
 180 template <class T>
 181 Fault
 182 CheckerCPU::read(Addr addr, T &data, unsigned flags)
 183 {
 184     // need to fill in CPU & thread IDs here
 185     memReq = new Request();
 186
 187     memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 188
 189     // translate to physical address
 190     translateDataReadReq(memReq);
 191
 192     Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
 193
 194     pkt->dataStatic(&data);
 195
 196     if (!(memReq->getFlags() & UNCACHEABLE)) {
 197         // Access memory to see if we have the same data
 198         dcachePort->sendFunctional(pkt);
 199     } else {
 200         // Assume the data is correct if it's an uncached access
 201         memcpy(&data, &unverifiedResult.integer, sizeof(T));
 202     }
 203
 204     delete pkt;
 205
 206     return NoFault;
 207 }
 208
 209 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 210
 211 template
 212 Fault
 213 CheckerCPU::read(Addr addr, uint64_t &data, unsigned flags);
 214
 215 template
 216 Fault
 217 CheckerCPU::read(Addr addr, uint32_t &data, unsigned flags);
 218
 219 template
 220 Fault
 221 CheckerCPU::read(Addr addr, uint16_t &data, unsigned flags);
 222
 223 template
 224 Fault
 225 CheckerCPU::read(Addr addr, uint8_t &data, unsigned flags);
 226
 227 #endif //DOXYGEN_SHOULD_SKIP_THIS
 228
 229 template<>
 230 Fault
 231 CheckerCPU::read(Addr addr, double &data, unsigned flags)
 232 {
 233     return read(addr, *(uint64_t*)&data, flags);
 234 }
 235
 236 template<>
 237 Fault
 238 CheckerCPU::read(Addr addr, float &data, unsigned flags)
 239 {
 240     return read(addr, *(uint32_t*)&data, flags);
 241 }
 242
 243 template<>
 244 Fault
 245 CheckerCPU::read(Addr addr, int32_t &data, unsigned flags)
 246 {
 247     return read(addr, (uint32_t&)data, flags);
 248 }
 249
 250 template <class T>
 251 Fault
 252 CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 253 {
 254     // need to fill in CPU & thread IDs here
 255     memReq = new Request();
 256
 257     memReq->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 258
 259     // translate to physical address
 260     thread->translateDataWriteReq(memReq);
 261
 262     // Can compare the write data and result only if it's cacheable,
 263     // not a store conditional, or is a store conditional that
 264     // succeeded.
 265     // @todo: Verify that actual memory matches up with these values.
 266     // Right now it only verifies that the instruction data is the
 267     // same as what was in the request that got sent to memory; there
 268     // is no verification that it is the same as what is in memory.
 269     // This is because the LSQ would have to be snooped in the CPU to
 270     // verify this data.
 271     if (unverifiedReq &&
 272         !(unverifiedReq->getFlags() & UNCACHEABLE) &&
 273         (!(unverifiedReq->getFlags() & LOCKED) ||
 274          ((unverifiedReq->getFlags() & LOCKED) &&
 275           unverifiedReq->getScResult() == 1))) {
 276         T inst_data;
 277 /*
 278         // This code would work if the LSQ allowed for snooping.
 279         Packet *pkt = new Packet(memReq, Packet::ReadReq, Packet::Broadcast);
 280         pkt.dataStatic(&inst_data);
 281
 282         dcachePort->sendFunctional(pkt);
 283
 284         delete pkt;
 285 */
 286         memcpy(&inst_data, unverifiedMemData, sizeof(T));
 287
 288         if (data != inst_data) {
 289             warn("%lli: Store value does not match value in memory! "
 290                  "Instruction: %#x, memory: %#x",
 291                  curTick, inst_data, data);
 292             handleError();
 293         }
 294     }
 295
 296     // Assume the result was the same as the one passed in.  This checker
 297     // doesn't check if the SC should succeed or fail, it just checks the
 298     // value.
 299     if (res && unverifiedReq->scResultValid())
 300         *res = unverifiedReq->getScResult();
 301
 302     return NoFault;
 303 }
 304
 305
 306 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 307 template
 308 Fault
 309 CheckerCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
 310
 311 template
 312 Fault
 313 CheckerCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
 314
 315 template
 316 Fault
 317 CheckerCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
 318
 319 template
 320 Fault
 321 CheckerCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
 322
 323 #endif //DOXYGEN_SHOULD_SKIP_THIS
 324
 325 template<>
 326 Fault
 327 CheckerCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 328 {
 329     return write(*(uint64_t*)&data, addr, flags, res);
 330 }
 331
 332 template<>
 333 Fault
 334 CheckerCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 335 {
 336     return write(*(uint32_t*)&data, addr, flags, res);
 337 }
 338
 339 template<>
 340 Fault
 341 CheckerCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 342 {
 343     return write((uint32_t)data, addr, flags, res);
 344 }
 345
 346
 347 #if FULL_SYSTEM
 348 Addr
 349 CheckerCPU::dbg_vtophys(Addr addr)
 350 {
 351     return vtophys(xcProxy, addr);
 352 }
 353 #endif // FULL_SYSTEM
 354
 355 bool
 356 CheckerCPU::translateInstReq(Request *req)
 357 {
 358 #if FULL_SYSTEM
 359     return (thread->translateInstReq(req) == NoFault);
 360 #else
 361     thread->translateInstReq(req);
 362     return true;
 363 #endif
 364 }
 365
 366 void
 367 CheckerCPU::translateDataReadReq(Request *req)
 368 {
 369     thread->translateDataReadReq(req);
 370
 371     if (req->getVaddr() != unverifiedReq->getVaddr()) {
 372         warn("%lli: Request virtual addresses do not match! Inst: %#x, "
 373              "checker: %#x",
 374              curTick, unverifiedReq->getVaddr(), req->getVaddr());
 375         handleError();
 376     }
 377     req->setPaddr(unverifiedReq->getPaddr());
 378
 379     if (checkFlags(req)) {
 380         warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
 381              curTick, unverifiedReq->getFlags(), req->getFlags());
 382         handleError();
 383     }
 384 }
 385
 386 void
 387 CheckerCPU::translateDataWriteReq(Request *req)
 388 {
 389     thread->translateDataWriteReq(req);
 390
 391     if (req->getVaddr() != unverifiedReq->getVaddr()) {
 392         warn("%lli: Request virtual addresses do not match! Inst: %#x, "
 393              "checker: %#x",
 394              curTick, unverifiedReq->getVaddr(), req->getVaddr());
 395         handleError();
 396     }
 397     req->setPaddr(unverifiedReq->getPaddr());
 398
 399     if (checkFlags(req)) {
 400         warn("%lli: Request flags do not match! Inst: %#x, checker: %#x",
 401              curTick, unverifiedReq->getFlags(), req->getFlags());
 402         handleError();
 403     }
 404 }
 405
 406 bool
 407 CheckerCPU::checkFlags(Request *req)
 408 {
 409     // Remove any dynamic flags that don't have to do with the request itself.
 410     unsigned flags = unverifiedReq->getFlags();
 411     unsigned mask = LOCKED | PHYSICAL | VPTE | ALTMODE | UNCACHEABLE | NO_FAULT;
 412     flags = flags & (mask);
 413     if (flags == req->getFlags()) {
 414         return false;
 415     } else {
 416         return true;
 417     }
 418 }
 419
 420 template <class DynInstPtr>
 421 void
 422 Checker<DynInstPtr>::tick(DynInstPtr &completed_inst)
 423 {
 424     DynInstPtr inst;
 425
 426     // Either check this instruction, or add it to a list of
 427     // instructions waiting to be checked.  Instructions must be
 428     // checked in program order, so if a store has committed yet not
 429     // completed, there may be some instructions that are waiting
 430     // behind it that have completed and must be checked.
 431     if (!instList.empty()) {
 432         if (youngestSN < completed_inst->seqNum) {
 433             DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
 434                     completed_inst->seqNum, completed_inst->readPC());
 435             instList.push_back(completed_inst);
 436             youngestSN = completed_inst->seqNum;
 437         }
 438
 439         if (!instList.front()->isCompleted()) {
 440             return;
 441         } else {
 442             inst = instList.front();
 443             instList.pop_front();
 444         }
 445     } else {
 446         if (!completed_inst->isCompleted()) {
 447             if (youngestSN < completed_inst->seqNum) {
 448                 DPRINTF(Checker, "Adding instruction [sn:%lli] PC:%#x to list.\n",
 449                         completed_inst->seqNum, completed_inst->readPC());
 450                 instList.push_back(completed_inst);
 451                 youngestSN = completed_inst->seqNum;
 452             }
 453             return;
 454         } else {
 455             if (youngestSN < completed_inst->seqNum) {
 456                 inst = completed_inst;
 457                 youngestSN = completed_inst->seqNum;
 458             } else {
 459                 return;
 460             }
 461         }
 462     }
 463
 464     // Try to check all instructions that are completed, ending if we
 465     // run out of instructions to check or if an instruction is not
 466     // yet completed.
 467     while (1) {
 468         DPRINTF(Checker, "Processing instruction [sn:%lli] PC:%#x.\n",
 469                 inst->seqNum, inst->readPC());
 470         unverifiedResult.integer = inst->readIntResult();
 471         unverifiedReq = inst->req;
 472         unverifiedMemData = inst->memData;
 473         numCycles++;
 474
 475         Fault fault = NoFault;
 476
 477         // maintain $r0 semantics
 478         thread->setIntReg(ZeroReg, 0);
 479 #ifdef TARGET_ALPHA
 480         thread->setFloatRegDouble(ZeroReg, 0.0);
 481 #endif // TARGET_ALPHA
 482
 483         // Check if any recent PC changes match up with anything we
 484         // expect to happen.  This is mostly to check if traps or
 485         // PC-based events have occurred in both the checker and CPU.
 486         if (changedPC) {
 487             DPRINTF(Checker, "Changed PC recently to %#x\n",
 488                     thread->readPC());
 489             if (willChangePC) {
 490                 if (newPC == thread->readPC()) {
 491                     DPRINTF(Checker, "Changed PC matches expected PC\n");
 492                 } else {
 493                     warn("%lli: Changed PC does not match expected PC, "
 494                          "changed: %#x, expected: %#x",
 495                          curTick, thread->readPC(), newPC);
 496                     handleError();
 497                 }
 498                 willChangePC = false;
 499             }
 500             changedPC = false;
 501         }
 502         if (changedNextPC) {
 503             DPRINTF(Checker, "Changed NextPC recently to %#x\n",
 504                     thread->readNextPC());
 505             changedNextPC = false;
 506         }
 507
 508         // Try to fetch the instruction
 509
 510 #if FULL_SYSTEM
 511 #define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 512 #else
 513 #define IFETCH_FLAGS(pc)        0
 514 #endif
 515
 516         uint64_t fetch_PC = thread->readPC() & ~3;
 517
 518         // set up memory request for instruction fetch
 519         memReq = new Request(inst->threadNumber, fetch_PC,
 520                              sizeof(uint32_t),
 521                              IFETCH_FLAGS(thread->readPC()),
 522                              fetch_PC, thread->readCpuId(), inst->threadNumber);
 523
 524         bool succeeded = translateInstReq(memReq);
 525
 526         if (!succeeded) {
 527             if (inst->getFault() == NoFault) {
 528                 // In this case the instruction was not a dummy
 529                 // instruction carrying an ITB fault.  In the single
 530                 // threaded case the ITB should still be able to
 531                 // translate this instruction; in the SMT case it's
 532                 // possible that its ITB entry was kicked out.
 533                 warn("%lli: Instruction PC %#x was not found in the ITB!",
 534                      curTick, thread->readPC());
 535                 handleError();
 536
 537                 // go to the next instruction
 538                 thread->setPC(thread->readNextPC());
 539                 thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 540
 541                 return;
 542             } else {
 543                 // The instruction is carrying an ITB fault.  Handle
 544                 // the fault and see if our results match the CPU on
 545                 // the next tick().
 546                 fault = inst->getFault();
 547             }
 548         }
 549
 550         if (fault == NoFault) {
 551             Packet *pkt = new Packet(memReq, Packet::ReadReq,
 552                                      Packet::Broadcast);
 553
 554             pkt->dataStatic(&machInst);
 555
 556             icachePort->sendFunctional(pkt);
 557
 558             delete pkt;
 559
 560             // keep an instruction count
 561             numInst++;
 562
 563             // decode the instruction
 564             machInst = gtoh(machInst);
 565             // Checks that the instruction matches what we expected it to be.
 566             // Checks both the machine instruction and the PC.
 567             validateInst(inst);
 568
 569             curStaticInst = StaticInst::decode(makeExtMI(machInst,
 570                                                          thread->readPC()));
 571
 572 #if FULL_SYSTEM
 573             thread->setInst(machInst);
 574 #endif // FULL_SYSTEM
 575
 576             fault = inst->getFault();
 577         }
 578
 579         // Discard fetch's memReq.
 580         delete memReq;
 581         memReq = NULL;
 582
 583         // Either the instruction was a fault and we should process the fault,
 584         // or we should just go ahead execute the instruction.  This assumes
 585         // that the instruction is properly marked as a fault.
 586         if (fault == NoFault) {
 587
 588             thread->funcExeInst++;
 589
 590             fault = curStaticInst->execute(this, NULL);
 591
 592             // Checks to make sure instrution results are correct.
 593             validateExecution(inst);
 594
 595             if (curStaticInst->isLoad()) {
 596                 ++numLoad;
 597             }
 598         }
 599
 600         if (fault != NoFault) {
 601 #if FULL_SYSTEM
 602             fault->invoke(xcProxy);
 603             willChangePC = true;
 604             newPC = thread->readPC();
 605             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
 606 #else // !FULL_SYSTEM
 607             fatal("fault (%d) detected @ PC 0x%08p", fault, thread->readPC());
 608 #endif // FULL_SYSTEM
 609         } else {
 610 #if THE_ISA != MIPS_ISA
 611             // go to the next instruction
 612             thread->setPC(thread->readNextPC());
 613             thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 614 #else
 615             // go to the next instruction
 616             thread->setPC(thread->readNextPC());
 617             thread->setNextPC(thread->readNextNPC());
 618             thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 619 #endif
 620
 621         }
 622
 623 #if FULL_SYSTEM
 624         // @todo: Determine if these should happen only if the
 625         // instruction hasn't faulted.  In the SimpleCPU case this may
 626         // not be true, but in the O3 or Ozone case this may be true.
 627         Addr oldpc;
 628         int count = 0;
 629         do {
 630             oldpc = thread->readPC();
 631             system->pcEventQueue.service(xcProxy);
 632             count++;
 633         } while (oldpc != thread->readPC());
 634         if (count > 1) {
 635             willChangePC = true;
 636             newPC = thread->readPC();
 637             DPRINTF(Checker, "PC Event, PC is now %#x\n", newPC);
 638         }
 639 #endif
 640
 641         // @todo:  Optionally can check all registers. (Or just those
 642         // that have been modified).
 643         validateState();
 644
 645         if (memReq) {
 646             delete memReq;
 647             memReq = NULL;
 648         }
 649
 650         // Continue verifying instructions if there's another completed
 651         // instruction waiting to be verified.
 652         if (instList.empty()) {
 653             break;
 654         } else if (instList.front()->isCompleted()) {
 655             inst = instList.front();
 656             instList.pop_front();
 657         } else {
 658             break;
 659         }
 660     }
 661 }
 662
 663 template <class DynInstPtr>
 664 void
 665 Checker<DynInstPtr>::switchOut(Sampler *s)
 666 {
 667     instList.clear();
 668 }
 669
 670 template <class DynInstPtr>
 671 void
 672 Checker<DynInstPtr>::takeOverFrom(BaseCPU *oldCPU)
 673 {
 674 }
 675
 676 template <class DynInstPtr>
 677 void
 678 Checker<DynInstPtr>::validateInst(DynInstPtr &inst)
 679 {
 680     if (inst->readPC() != thread->readPC()) {
 681         warn("%lli: PCs do not match! Inst: %#x, checker: %#x",
 682              curTick, inst->readPC(), thread->readPC());
 683         if (changedPC) {
 684             warn("%lli: Changed PCs recently, may not be an error",
 685                  curTick);
 686         } else {
 687             handleError();
 688         }
 689     }
 690
 691     MachInst mi = static_cast<MachInst>(inst->staticInst->machInst);
 692
 693     if (mi != machInst) {
 694         warn("%lli: Binary instructions do not match! Inst: %#x, "
 695              "checker: %#x",
 696              curTick, mi, machInst);
 697         handleError();
 698     }
 699 }
 700
 701 template <class DynInstPtr>
 702 void
 703 Checker<DynInstPtr>::validateExecution(DynInstPtr &inst)
 704 {
 705     if (inst->numDestRegs()) {
 706         // @todo: Support more destination registers.
 707         if (inst->isUnverifiable()) {
 708             // Unverifiable instructions assume they were executed
 709             // properly by the CPU. Grab the result from the
 710             // instruction and write it to the register.
 711             RegIndex idx = inst->destRegIdx(0);
 712             if (idx < TheISA::FP_Base_DepTag) {
 713                 thread->setIntReg(idx, inst->readIntResult());
 714             } else if (idx < TheISA::Fpcr_DepTag) {
 715                 thread->setFloatRegBits(idx, inst->readIntResult());
 716             } else {
 717                 thread->setMiscReg(idx, inst->readIntResult());
 718             }
 719         } else if (result.integer != inst->readIntResult()) {
 720             warn("%lli: Instruction results do not match! (Values may not "
 721                  "actually be integers) Inst: %#x, checker: %#x",
 722                  curTick, inst->readIntResult(), result.integer);
 723             handleError();
 724         }
 725     }
 726
 727     if (inst->readNextPC() != thread->readNextPC()) {
 728         warn("%lli: Instruction next PCs do not match! Inst: %#x, "
 729              "checker: %#x",
 730              curTick, inst->readNextPC(), thread->readNextPC());
 731         handleError();
 732     }
 733
 734     // Checking side effect registers can be difficult if they are not
 735     // checked simultaneously with the execution of the instruction.
 736     // This is because other valid instructions may have modified
 737     // these registers in the meantime, and their values are not
 738     // stored within the DynInst.
 739     while (!miscRegIdxs.empty()) {
 740         int misc_reg_idx = miscRegIdxs.front();
 741         miscRegIdxs.pop();
 742
 743         if (inst->tcBase()->readMiscReg(misc_reg_idx) !=
 744             thread->readMiscReg(misc_reg_idx)) {
 745             warn("%lli: Misc reg idx %i (side effect) does not match! "
 746                  "Inst: %#x, checker: %#x",
 747                  curTick, misc_reg_idx,
 748                  inst->tcBase()->readMiscReg(misc_reg_idx),
 749                  thread->readMiscReg(misc_reg_idx));
 750             handleError();
 751         }
 752     }
 753 }
 754
 755 template <class DynInstPtr>
 756 void
 757 Checker<DynInstPtr>::validateState()
 758 {
 759 }
 760
 761 template <class DynInstPtr>
 762 void
 763 Checker<DynInstPtr>::dumpInsts()
 764 {
 765     int num = 0;
 766
 767     InstListIt inst_list_it = --(instList.end());
 768
 769     cprintf("Inst list size: %i\n", instList.size());
 770
 771     while (inst_list_it != instList.end())
 772     {
 773         cprintf("Instruction:%i\n",
 774                 num);
 775
 776         cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
 777                 "Completed:%i\n",
 778                 (*inst_list_it)->readPC(),
 779                 (*inst_list_it)->seqNum,
 780                 (*inst_list_it)->threadNumber,
 781                 (*inst_list_it)->isCompleted());
 782
 783         cprintf("\n");
 784
 785         inst_list_it--;
 786         ++num;
 787     }
 788
 789 }
 790
 791 //template
 792 //class Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >;
 793
 794 template
 795 class Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >;