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47 #include "arch/generic/tlb.hh"
48 #include "arch/kernel_stats.hh"
49 #include "arch/vtophys.hh"
50 #include "cpu/checker/cpu.hh"
51 #include "cpu/base.hh"
52 #include "cpu/simple_thread.hh"
53 #include "cpu/static_inst.hh"
54 #include "cpu/thread_context.hh"
55 #include "params/CheckerCPU.hh"
56 #include "sim/full_system.hh"
59 using namespace TheISA
;
64 masterId
= systemPtr
->getMasterId(name());
67 CheckerCPU::CheckerCPU(Params
*p
)
68 : BaseCPU(p
, true), systemPtr(NULL
), icachePort(NULL
), dcachePort(NULL
),
69 tc(NULL
), thread(NULL
)
73 curMacroStaticInst
= NULL
;
81 changedPC
= willChangePC
= false;
83 exitOnError
= p
->exitOnError
;
84 warnOnlyOnLoadError
= p
->warnOnlyOnLoadError
;
87 workload
= p
->workload
;
92 CheckerCPU::~CheckerCPU()
97 CheckerCPU::setSystem(System
*system
)
99 const Params
*p(dynamic_cast<const Params
*>(_params
));
104 thread
= new SimpleThread(this, 0, systemPtr
, itb
, dtb
,
107 thread
= new SimpleThread(this, 0, systemPtr
,
108 workload
.size() ? workload
[0] : NULL
,
109 itb
, dtb
, p
->isa
[0]);
112 tc
= thread
->getTC();
113 threadContexts
.push_back(tc
);
114 thread
->kernelStats
= NULL
;
115 // Thread should never be null after this
116 assert(thread
!= NULL
);
120 CheckerCPU::setIcachePort(MasterPort
*icache_port
)
122 icachePort
= icache_port
;
126 CheckerCPU::setDcachePort(MasterPort
*dcache_port
)
128 dcachePort
= dcache_port
;
132 CheckerCPU::serialize(ostream
&os
)
137 CheckerCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
142 CheckerCPU::readMem(Addr addr
, uint8_t *data
, unsigned size
, unsigned flags
)
144 Fault fault
= NoFault
;
146 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
147 bool checked_flags
= false;
148 bool flags_match
= true;
152 if (secondAddr
> addr
)
153 size
= secondAddr
- addr
;
155 // Need to account for multiple accesses like the Atomic and TimingSimple
157 memReq
= new Request(0, addr
, size
, flags
, masterId
,
158 thread
->pcState().instAddr(), tc
->contextId(), 0);
160 // translate to physical address
161 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Read
);
163 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
164 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
165 memReq
->getPaddr(), memReq
->getFlags());
166 pAddr
= memReq
->getPaddr();
167 checked_flags
= true;
171 if (fault
== NoFault
&&
172 !memReq
->getFlags().isSet(Request::NO_ACCESS
)) {
173 PacketPtr pkt
= Packet::createRead(memReq
);
175 pkt
->dataStatic(data
);
177 if (!(memReq
->isUncacheable() || memReq
->isMmappedIpr())) {
178 // Access memory to see if we have the same data
179 dcachePort
->sendFunctional(pkt
);
181 // Assume the data is correct if it's an uncached access
182 memcpy(data
, unverifiedMemData
, size
);
190 if (fault
!= NoFault
) {
191 if (memReq
->isPrefetch()) {
199 if (memReq
!= NULL
) {
203 //If we don't need to access a second cache line, stop now.
204 if (secondAddr
<= addr
)
209 // Setup for accessing next cache line
211 unverifiedMemData
+= size
;
212 size
= addr
+ fullSize
- secondAddr
;
217 warn("%lli: Flags do not match CPU:%#x %#x %#x Checker:%#x %#x %#x\n",
218 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
219 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
227 CheckerCPU::writeMem(uint8_t *data
, unsigned size
,
228 Addr addr
, unsigned flags
, uint64_t *res
)
230 Fault fault
= NoFault
;
231 bool checked_flags
= false;
232 bool flags_match
= true;
234 static uint8_t zero_data
[64] = {};
238 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
240 if (secondAddr
> addr
)
241 size
= secondAddr
- addr
;
243 // Need to account for a multiple access like Atomic and Timing CPUs
245 memReq
= new Request(0, addr
, size
, flags
, masterId
,
246 thread
->pcState().instAddr(), tc
->contextId(), 0);
248 // translate to physical address
249 fault
= dtb
->translateFunctional(memReq
, tc
, BaseTLB::Write
);
251 if (!checked_flags
&& fault
== NoFault
&& unverifiedReq
) {
252 flags_match
= checkFlags(unverifiedReq
, memReq
->getVaddr(),
253 memReq
->getPaddr(), memReq
->getFlags());
254 pAddr
= memReq
->getPaddr();
255 checked_flags
= true;
259 * We don't actually check memory for the store because there
260 * is no guarantee it has left the lsq yet, and therefore we
261 * can't verify the memory on stores without lsq snooping
262 * enabled. This is left as future work for the Checker: LSQ snooping
263 * and memory validation after stores have committed.
265 bool was_prefetch
= memReq
->isPrefetch();
269 //If we don't need to access a second cache line, stop now.
270 if (fault
!= NoFault
|| secondAddr
<= addr
)
272 if (fault
!= NoFault
&& was_prefetch
) {
278 //Update size and access address
279 size
= addr
+ fullSize
- secondAddr
;
280 //And access the right address.
285 warn("%lli: Flags do not match CPU:%#x %#x Checker:%#x %#x %#x\n",
286 curTick(), unverifiedReq
->getVaddr(), unverifiedReq
->getPaddr(),
287 unverifiedReq
->getFlags(), addr
, pAddr
, flags
);
291 // Assume the result was the same as the one passed in. This checker
292 // doesn't check if the SC should succeed or fail, it just checks the
294 if (unverifiedReq
&& res
&& unverifiedReq
->extraDataValid())
295 *res
= unverifiedReq
->getExtraData();
297 // Entire purpose here is to make sure we are getting the
298 // same data to send to the mem system as the CPU did.
299 // Cannot check this is actually what went to memory because
300 // there stores can be in ld/st queue or coherent operations
301 // overwriting values.
302 bool extraData
= false;
304 extraData
= unverifiedReq
->extraDataValid() ?
305 unverifiedReq
->getExtraData() : true;
308 // If the request is to ZERO a cache block, there is no data to check
309 // against, but it's all zero. We need something to compare to, so use a
310 // const set of zeros.
311 if (flags
& Request::CACHE_BLOCK_ZERO
) {
313 assert(sizeof(zero_data
) <= fullSize
);
317 if (unverifiedReq
&& unverifiedMemData
&&
318 memcmp(data
, unverifiedMemData
, fullSize
) && extraData
) {
319 warn("%lli: Store value does not match value sent to memory! "
320 "data: %#x inst_data: %#x", curTick(), data
,
329 CheckerCPU::dbg_vtophys(Addr addr
)
331 return vtophys(tc
, addr
);
335 * Checks if the flags set by the Checker and Checkee match.
338 CheckerCPU::checkFlags(Request
*unverified_req
, Addr vAddr
,
339 Addr pAddr
, int flags
)
341 Addr unverifiedVAddr
= unverified_req
->getVaddr();
342 Addr unverifiedPAddr
= unverified_req
->getPaddr();
343 int unverifiedFlags
= unverified_req
->getFlags();
345 if (unverifiedVAddr
!= vAddr
||
346 unverifiedPAddr
!= pAddr
||
347 unverifiedFlags
!= flags
) {
355 CheckerCPU::dumpAndExit()
357 warn("%lli: Checker PC:%s",
358 curTick(), thread
->pcState());
359 panic("Checker found an error!");